Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8252573 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4780 |
| auto[1] |
6188464 |
1 |
|
|
T1 |
3829 |
|
T12 |
87 |
|
T2 |
21529 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13648221 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8134 |
| auto[1] |
792816 |
1 |
|
|
T1 |
475 |
|
T12 |
9 |
|
T2 |
2888 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8268737 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
5117 |
| auto[1] |
6172300 |
1 |
|
|
T1 |
3492 |
|
T12 |
128 |
|
T2 |
21307 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2681949 |
1 |
|
|
T1 |
836 |
|
T12 |
55 |
|
T2 |
9029 |
| auto[1] |
auto[0] |
auto[1] |
394924 |
1 |
|
|
T1 |
118 |
|
T12 |
4 |
|
T2 |
1368 |
| auto[1] |
auto[1] |
auto[0] |
2697535 |
1 |
|
|
T1 |
2181 |
|
T12 |
64 |
|
T2 |
9390 |
| auto[1] |
auto[1] |
auto[1] |
397892 |
1 |
|
|
T1 |
357 |
|
T12 |
5 |
|
T2 |
1520 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8233147 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6280 |
| auto[1] |
6207890 |
1 |
|
|
T1 |
2329 |
|
T12 |
88 |
|
T2 |
21886 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13646327 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8116 |
| auto[1] |
794710 |
1 |
|
|
T1 |
493 |
|
T12 |
3 |
|
T2 |
2438 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8272294 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4824 |
| auto[1] |
6168743 |
1 |
|
|
T1 |
3785 |
|
T12 |
52 |
|
T2 |
19265 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2686101 |
1 |
|
|
T1 |
2184 |
|
T12 |
32 |
|
T2 |
8173 |
| auto[1] |
auto[0] |
auto[1] |
396930 |
1 |
|
|
T1 |
335 |
|
T12 |
2 |
|
T2 |
1208 |
| auto[1] |
auto[1] |
auto[0] |
2687932 |
1 |
|
|
T1 |
1108 |
|
T12 |
17 |
|
T2 |
8654 |
| auto[1] |
auto[1] |
auto[1] |
397780 |
1 |
|
|
T1 |
158 |
|
T12 |
1 |
|
T2 |
1230 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8217287 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6221 |
| auto[1] |
6223750 |
1 |
|
|
T1 |
2388 |
|
T12 |
99 |
|
T2 |
19929 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13644236 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8341 |
| auto[1] |
796801 |
1 |
|
|
T1 |
268 |
|
T12 |
6 |
|
T2 |
2667 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8255096 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6510 |
| auto[1] |
6185941 |
1 |
|
|
T1 |
2099 |
|
T12 |
115 |
|
T2 |
20700 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2673893 |
1 |
|
|
T1 |
959 |
|
T12 |
54 |
|
T2 |
9189 |
| auto[1] |
auto[0] |
auto[1] |
394229 |
1 |
|
|
T1 |
142 |
|
T12 |
4 |
|
T2 |
1355 |
| auto[1] |
auto[1] |
auto[0] |
2715247 |
1 |
|
|
T1 |
872 |
|
T12 |
55 |
|
T2 |
8844 |
| auto[1] |
auto[1] |
auto[1] |
402572 |
1 |
|
|
T1 |
126 |
|
T12 |
2 |
|
T2 |
1312 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8239789 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
5155 |
| auto[1] |
6201248 |
1 |
|
|
T1 |
3454 |
|
T12 |
136 |
|
T2 |
20276 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13644672 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8350 |
| auto[1] |
796365 |
1 |
|
|
T1 |
259 |
|
T12 |
3 |
|
T2 |
3047 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8261773 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6494 |
| auto[1] |
6179264 |
1 |
|
|
T1 |
2115 |
|
T12 |
68 |
|
T2 |
22292 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2687540 |
1 |
|
|
T1 |
1094 |
|
T12 |
13 |
|
T2 |
9318 |
| auto[1] |
auto[0] |
auto[1] |
398018 |
1 |
|
|
T1 |
145 |
|
T12 |
1 |
|
T2 |
1529 |
| auto[1] |
auto[1] |
auto[0] |
2695359 |
1 |
|
|
T1 |
762 |
|
T12 |
52 |
|
T2 |
9927 |
| auto[1] |
auto[1] |
auto[1] |
398347 |
1 |
|
|
T1 |
114 |
|
T12 |
2 |
|
T2 |
1518 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8292624 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6438 |
| auto[1] |
6148413 |
1 |
|
|
T1 |
2171 |
|
T12 |
100 |
|
T2 |
19442 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13647034 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8077 |
| auto[1] |
794003 |
1 |
|
|
T1 |
532 |
|
T12 |
3 |
|
T2 |
2711 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8263659 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4767 |
| auto[1] |
6177378 |
1 |
|
|
T1 |
3842 |
|
T12 |
81 |
|
T2 |
20850 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2700787 |
1 |
|
|
T1 |
2272 |
|
T12 |
29 |
|
T2 |
9918 |
| auto[1] |
auto[0] |
auto[1] |
400441 |
1 |
|
|
T1 |
364 |
|
T12 |
2 |
|
T2 |
1590 |
| auto[1] |
auto[1] |
auto[0] |
2682588 |
1 |
|
|
T1 |
1038 |
|
T12 |
49 |
|
T2 |
8221 |
| auto[1] |
auto[1] |
auto[1] |
393562 |
1 |
|
|
T1 |
168 |
|
T12 |
1 |
|
T2 |
1121 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8235985 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6278 |
| auto[1] |
6205052 |
1 |
|
|
T1 |
2331 |
|
T12 |
125 |
|
T2 |
21772 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13646068 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8348 |
| auto[1] |
794969 |
1 |
|
|
T1 |
261 |
|
T12 |
5 |
|
T2 |
2555 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8263252 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6510 |
| auto[1] |
6177785 |
1 |
|
|
T1 |
2099 |
|
T12 |
82 |
|
T2 |
19676 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2696236 |
1 |
|
|
T1 |
843 |
|
T12 |
37 |
|
T2 |
8346 |
| auto[1] |
auto[0] |
auto[1] |
397671 |
1 |
|
|
T1 |
125 |
|
T12 |
2 |
|
T2 |
1199 |
| auto[1] |
auto[1] |
auto[0] |
2686580 |
1 |
|
|
T1 |
995 |
|
T12 |
40 |
|
T2 |
8775 |
| auto[1] |
auto[1] |
auto[1] |
397298 |
1 |
|
|
T1 |
136 |
|
T12 |
3 |
|
T2 |
1356 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8309487 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6778 |
| auto[1] |
6131550 |
1 |
|
|
T1 |
1831 |
|
T12 |
107 |
|
T2 |
21692 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13641767 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8125 |
| auto[1] |
799270 |
1 |
|
|
T1 |
484 |
|
T12 |
5 |
|
T2 |
2834 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8244647 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
5080 |
| auto[1] |
6196390 |
1 |
|
|
T1 |
3529 |
|
T12 |
87 |
|
T2 |
21850 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2734702 |
1 |
|
|
T1 |
2405 |
|
T12 |
43 |
|
T2 |
8485 |
| auto[1] |
auto[0] |
auto[1] |
405900 |
1 |
|
|
T1 |
398 |
|
T12 |
2 |
|
T2 |
1242 |
| auto[1] |
auto[1] |
auto[0] |
2662418 |
1 |
|
|
T1 |
640 |
|
T12 |
39 |
|
T2 |
10531 |
| auto[1] |
auto[1] |
auto[1] |
393370 |
1 |
|
|
T1 |
86 |
|
T12 |
3 |
|
T2 |
1592 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8266820 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4977 |
| auto[1] |
6174217 |
1 |
|
|
T1 |
3632 |
|
T12 |
77 |
|
T2 |
22177 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13643485 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8325 |
| auto[1] |
797552 |
1 |
|
|
T1 |
284 |
|
T12 |
4 |
|
T2 |
2897 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8252021 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6364 |
| auto[1] |
6189016 |
1 |
|
|
T1 |
2245 |
|
T12 |
93 |
|
T2 |
22047 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2702158 |
1 |
|
|
T1 |
1056 |
|
T12 |
52 |
|
T2 |
8666 |
| auto[1] |
auto[0] |
auto[1] |
399959 |
1 |
|
|
T1 |
176 |
|
T12 |
4 |
|
T2 |
1298 |
| auto[1] |
auto[1] |
auto[0] |
2689306 |
1 |
|
|
T1 |
905 |
|
T12 |
37 |
|
T2 |
10484 |
| auto[1] |
auto[1] |
auto[1] |
397593 |
1 |
|
|
T1 |
108 |
|
T2 |
1599 |
|
T13 |
11323 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8234755 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6637 |
| auto[1] |
6206282 |
1 |
|
|
T1 |
1972 |
|
T12 |
96 |
|
T2 |
21662 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13642906 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8341 |
| auto[1] |
798131 |
1 |
|
|
T1 |
268 |
|
T12 |
5 |
|
T2 |
2648 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8244129 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6501 |
| auto[1] |
6196908 |
1 |
|
|
T1 |
2108 |
|
T12 |
99 |
|
T2 |
20413 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2696236 |
1 |
|
|
T1 |
957 |
|
T12 |
50 |
|
T2 |
8128 |
| auto[1] |
auto[0] |
auto[1] |
397648 |
1 |
|
|
T1 |
147 |
|
T12 |
3 |
|
T2 |
1165 |
| auto[1] |
auto[1] |
auto[0] |
2702541 |
1 |
|
|
T1 |
883 |
|
T12 |
44 |
|
T2 |
9637 |
| auto[1] |
auto[1] |
auto[1] |
400483 |
1 |
|
|
T1 |
121 |
|
T12 |
2 |
|
T2 |
1483 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8229327 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4973 |
| auto[1] |
6211710 |
1 |
|
|
T1 |
3636 |
|
T12 |
108 |
|
T2 |
20247 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13645097 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8321 |
| auto[1] |
795940 |
1 |
|
|
T1 |
288 |
|
T12 |
8 |
|
T2 |
2872 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8259548 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6277 |
| auto[1] |
6181489 |
1 |
|
|
T1 |
2332 |
|
T12 |
140 |
|
T2 |
21583 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2673490 |
1 |
|
|
T1 |
1119 |
|
T12 |
68 |
|
T2 |
10074 |
| auto[1] |
auto[0] |
auto[1] |
394530 |
1 |
|
|
T1 |
152 |
|
T12 |
3 |
|
T2 |
1485 |
| auto[1] |
auto[1] |
auto[0] |
2712059 |
1 |
|
|
T1 |
925 |
|
T12 |
64 |
|
T2 |
8637 |
| auto[1] |
auto[1] |
auto[1] |
401410 |
1 |
|
|
T1 |
136 |
|
T12 |
5 |
|
T2 |
1387 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8256844 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4742 |
| auto[1] |
6184193 |
1 |
|
|
T1 |
3867 |
|
T12 |
134 |
|
T2 |
21442 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13642278 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8091 |
| auto[1] |
798759 |
1 |
|
|
T1 |
518 |
|
T12 |
2 |
|
T2 |
2573 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8249697 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4715 |
| auto[1] |
6191340 |
1 |
|
|
T1 |
3894 |
|
T12 |
67 |
|
T2 |
19940 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2691385 |
1 |
|
|
T1 |
992 |
|
T12 |
20 |
|
T2 |
7928 |
| auto[1] |
auto[0] |
auto[1] |
399510 |
1 |
|
|
T1 |
132 |
|
T12 |
1 |
|
T2 |
1141 |
| auto[1] |
auto[1] |
auto[0] |
2701196 |
1 |
|
|
T1 |
2384 |
|
T12 |
45 |
|
T2 |
9439 |
| auto[1] |
auto[1] |
auto[1] |
399249 |
1 |
|
|
T1 |
386 |
|
T12 |
1 |
|
T2 |
1432 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8230561 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6616 |
| auto[1] |
6210476 |
1 |
|
|
T1 |
1993 |
|
T12 |
67 |
|
T2 |
21012 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13648140 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8093 |
| auto[1] |
792897 |
1 |
|
|
T1 |
516 |
|
T12 |
4 |
|
T2 |
2614 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8276123 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
5025 |
| auto[1] |
6164914 |
1 |
|
|
T1 |
3584 |
|
T12 |
72 |
|
T2 |
20263 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2675366 |
1 |
|
|
T1 |
2260 |
|
T12 |
52 |
|
T2 |
8273 |
| auto[1] |
auto[0] |
auto[1] |
394229 |
1 |
|
|
T1 |
401 |
|
T12 |
4 |
|
T2 |
1231 |
| auto[1] |
auto[1] |
auto[0] |
2696651 |
1 |
|
|
T1 |
808 |
|
T12 |
16 |
|
T2 |
9376 |
| auto[1] |
auto[1] |
auto[1] |
398668 |
1 |
|
|
T1 |
115 |
|
T2 |
1383 |
|
T13 |
11334 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8278731 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6622 |
| auto[1] |
6162306 |
1 |
|
|
T1 |
1987 |
|
T12 |
123 |
|
T2 |
19540 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13641743 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8146 |
| auto[1] |
799294 |
1 |
|
|
T1 |
463 |
|
T12 |
7 |
|
T2 |
2527 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8235265 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
5053 |
| auto[1] |
6205772 |
1 |
|
|
T1 |
3556 |
|
T12 |
101 |
|
T2 |
19697 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2716386 |
1 |
|
|
T1 |
2306 |
|
T12 |
41 |
|
T2 |
9002 |
| auto[1] |
auto[0] |
auto[1] |
402206 |
1 |
|
|
T1 |
370 |
|
T12 |
2 |
|
T2 |
1398 |
| auto[1] |
auto[1] |
auto[0] |
2690092 |
1 |
|
|
T1 |
787 |
|
T12 |
53 |
|
T2 |
8168 |
| auto[1] |
auto[1] |
auto[1] |
397088 |
1 |
|
|
T1 |
93 |
|
T12 |
5 |
|
T2 |
1129 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8247897 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6627 |
| auto[1] |
6193140 |
1 |
|
|
T1 |
1982 |
|
T12 |
63 |
|
T2 |
20524 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13647991 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8371 |
| auto[1] |
793046 |
1 |
|
|
T1 |
238 |
|
T12 |
7 |
|
T2 |
2629 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8272509 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6674 |
| auto[1] |
6168528 |
1 |
|
|
T1 |
1935 |
|
T12 |
78 |
|
T2 |
20403 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2684154 |
1 |
|
|
T1 |
891 |
|
T12 |
44 |
|
T2 |
9106 |
| auto[1] |
auto[0] |
auto[1] |
396530 |
1 |
|
|
T1 |
116 |
|
T12 |
3 |
|
T2 |
1347 |
| auto[1] |
auto[1] |
auto[0] |
2691328 |
1 |
|
|
T1 |
806 |
|
T12 |
27 |
|
T2 |
8668 |
| auto[1] |
auto[1] |
auto[1] |
396516 |
1 |
|
|
T1 |
122 |
|
T12 |
4 |
|
T2 |
1282 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8255153 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4709 |
| auto[1] |
6185884 |
1 |
|
|
T1 |
3900 |
|
T12 |
113 |
|
T2 |
21017 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13644280 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8347 |
| auto[1] |
796757 |
1 |
|
|
T1 |
262 |
|
T12 |
4 |
|
T2 |
2706 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8254356 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6407 |
| auto[1] |
6186681 |
1 |
|
|
T1 |
2202 |
|
T12 |
125 |
|
T2 |
21348 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2689340 |
1 |
|
|
T1 |
901 |
|
T12 |
43 |
|
T2 |
8733 |
| auto[1] |
auto[0] |
auto[1] |
397444 |
1 |
|
|
T1 |
146 |
|
T12 |
2 |
|
T2 |
1289 |
| auto[1] |
auto[1] |
auto[0] |
2700584 |
1 |
|
|
T1 |
1039 |
|
T12 |
78 |
|
T2 |
9909 |
| auto[1] |
auto[1] |
auto[1] |
399313 |
1 |
|
|
T1 |
116 |
|
T12 |
2 |
|
T2 |
1417 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8268265 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4987 |
| auto[1] |
6172772 |
1 |
|
|
T1 |
3622 |
|
T12 |
91 |
|
T2 |
19982 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13646198 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8323 |
| auto[1] |
794839 |
1 |
|
|
T1 |
286 |
|
T12 |
7 |
|
T2 |
2918 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8271084 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6422 |
| auto[1] |
6169953 |
1 |
|
|
T1 |
2187 |
|
T12 |
81 |
|
T2 |
22051 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2696616 |
1 |
|
|
T1 |
1046 |
|
T12 |
39 |
|
T2 |
10338 |
| auto[1] |
auto[0] |
auto[1] |
398691 |
1 |
|
|
T1 |
154 |
|
T12 |
6 |
|
T2 |
1638 |
| auto[1] |
auto[1] |
auto[0] |
2678498 |
1 |
|
|
T1 |
855 |
|
T12 |
35 |
|
T2 |
8795 |
| auto[1] |
auto[1] |
auto[1] |
396148 |
1 |
|
|
T1 |
132 |
|
T12 |
1 |
|
T2 |
1280 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8277650 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6498 |
| auto[1] |
6163387 |
1 |
|
|
T1 |
2111 |
|
T12 |
106 |
|
T2 |
21944 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13647407 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8408 |
| auto[1] |
793630 |
1 |
|
|
T1 |
201 |
|
T12 |
6 |
|
T2 |
2591 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8273068 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6853 |
| auto[1] |
6167969 |
1 |
|
|
T1 |
1756 |
|
T12 |
112 |
|
T2 |
19975 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2692793 |
1 |
|
|
T1 |
748 |
|
T12 |
64 |
|
T2 |
8438 |
| auto[1] |
auto[0] |
auto[1] |
397145 |
1 |
|
|
T1 |
90 |
|
T12 |
3 |
|
T2 |
1272 |
| auto[1] |
auto[1] |
auto[0] |
2681546 |
1 |
|
|
T1 |
807 |
|
T12 |
42 |
|
T2 |
8946 |
| auto[1] |
auto[1] |
auto[1] |
396485 |
1 |
|
|
T1 |
111 |
|
T12 |
3 |
|
T2 |
1319 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8253724 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4924 |
| auto[1] |
6187313 |
1 |
|
|
T1 |
3685 |
|
T12 |
152 |
|
T2 |
19775 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13645544 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8300 |
| auto[1] |
795493 |
1 |
|
|
T1 |
309 |
|
T12 |
1 |
|
T2 |
2637 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8271397 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6127 |
| auto[1] |
6169640 |
1 |
|
|
T1 |
2482 |
|
T12 |
45 |
|
T2 |
20903 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2676716 |
1 |
|
|
T1 |
1221 |
|
T12 |
14 |
|
T2 |
10233 |
| auto[1] |
auto[0] |
auto[1] |
395350 |
1 |
|
|
T1 |
169 |
|
T2 |
1515 |
|
T13 |
10535 |
| auto[1] |
auto[1] |
auto[0] |
2697431 |
1 |
|
|
T1 |
952 |
|
T12 |
30 |
|
T2 |
8033 |
| auto[1] |
auto[1] |
auto[1] |
400143 |
1 |
|
|
T1 |
140 |
|
T12 |
1 |
|
T2 |
1122 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8260516 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4559 |
| auto[1] |
6180521 |
1 |
|
|
T1 |
4050 |
|
T12 |
75 |
|
T2 |
21162 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13643678 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8309 |
| auto[1] |
797359 |
1 |
|
|
T1 |
300 |
|
T12 |
7 |
|
T2 |
2886 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8252066 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6263 |
| auto[1] |
6188971 |
1 |
|
|
T1 |
2346 |
|
T12 |
120 |
|
T2 |
21607 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2692027 |
1 |
|
|
T1 |
907 |
|
T12 |
58 |
|
T2 |
9192 |
| auto[1] |
auto[0] |
auto[1] |
398011 |
1 |
|
|
T1 |
144 |
|
T12 |
3 |
|
T2 |
1454 |
| auto[1] |
auto[1] |
auto[0] |
2699585 |
1 |
|
|
T1 |
1139 |
|
T12 |
55 |
|
T2 |
9529 |
| auto[1] |
auto[1] |
auto[1] |
399348 |
1 |
|
|
T1 |
156 |
|
T12 |
4 |
|
T2 |
1432 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8234773 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4864 |
| auto[1] |
6206264 |
1 |
|
|
T1 |
3745 |
|
T12 |
67 |
|
T2 |
21184 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13646921 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8295 |
| auto[1] |
794116 |
1 |
|
|
T1 |
314 |
|
T12 |
6 |
|
T2 |
2692 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8263775 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6282 |
| auto[1] |
6177262 |
1 |
|
|
T1 |
2327 |
|
T12 |
115 |
|
T2 |
20825 |