Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8256096 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4656 |
| auto[1] |
6184941 |
1 |
|
|
T1 |
3953 |
|
T12 |
122 |
|
T2 |
21516 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13644508 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8089 |
| auto[1] |
796529 |
1 |
|
|
T1 |
520 |
|
T12 |
10 |
|
T2 |
2738 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8254105 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4964 |
| auto[1] |
6186932 |
1 |
|
|
T1 |
3645 |
|
T12 |
118 |
|
T2 |
21343 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2707726 |
1 |
|
|
T1 |
760 |
|
T12 |
44 |
|
T2 |
8684 |
| auto[1] |
auto[0] |
auto[1] |
400430 |
1 |
|
|
T1 |
108 |
|
T12 |
5 |
|
T2 |
1240 |
| auto[1] |
auto[1] |
auto[0] |
2682677 |
1 |
|
|
T1 |
2365 |
|
T12 |
64 |
|
T2 |
9921 |
| auto[1] |
auto[1] |
auto[1] |
396099 |
1 |
|
|
T1 |
412 |
|
T12 |
5 |
|
T2 |
1498 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |