Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8228792 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4724 |
| auto[1] |
6212245 |
1 |
|
|
T1 |
3885 |
|
T12 |
75 |
|
T2 |
21133 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13641535 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8381 |
| auto[1] |
799502 |
1 |
|
|
T1 |
228 |
|
T12 |
2 |
|
T2 |
2857 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8242762 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6781 |
| auto[1] |
6198275 |
1 |
|
|
T1 |
1828 |
|
T12 |
66 |
|
T2 |
22129 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2693008 |
1 |
|
|
T1 |
787 |
|
T12 |
35 |
|
T2 |
9803 |
| auto[1] |
auto[0] |
auto[1] |
398179 |
1 |
|
|
T1 |
121 |
|
T2 |
1432 |
|
T13 |
10602 |
| auto[1] |
auto[1] |
auto[0] |
2705765 |
1 |
|
|
T1 |
813 |
|
T12 |
29 |
|
T2 |
9469 |
| auto[1] |
auto[1] |
auto[1] |
401323 |
1 |
|
|
T1 |
107 |
|
T12 |
2 |
|
T2 |
1425 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |