Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8238187 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6187 |
| auto[1] |
6202850 |
1 |
|
|
T1 |
2422 |
|
T12 |
112 |
|
T2 |
20215 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13642212 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8306 |
| auto[1] |
798825 |
1 |
|
|
T1 |
303 |
|
T12 |
5 |
|
T2 |
2533 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8240396 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6368 |
| auto[1] |
6200641 |
1 |
|
|
T1 |
2241 |
|
T12 |
106 |
|
T2 |
19446 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2689966 |
1 |
|
|
T1 |
851 |
|
T12 |
57 |
|
T2 |
8641 |
| auto[1] |
auto[0] |
auto[1] |
396735 |
1 |
|
|
T1 |
135 |
|
T12 |
3 |
|
T2 |
1357 |
| auto[1] |
auto[1] |
auto[0] |
2711850 |
1 |
|
|
T1 |
1087 |
|
T12 |
44 |
|
T2 |
8272 |
| auto[1] |
auto[1] |
auto[1] |
402090 |
1 |
|
|
T1 |
168 |
|
T12 |
2 |
|
T2 |
1176 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |