Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8213323 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
5131 |
| auto[1] |
6227714 |
1 |
|
|
T1 |
3478 |
|
T12 |
104 |
|
T2 |
20678 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13647193 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8028 |
| auto[1] |
793844 |
1 |
|
|
T1 |
581 |
|
T12 |
6 |
|
T2 |
2824 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8276859 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4310 |
| auto[1] |
6164178 |
1 |
|
|
T1 |
4299 |
|
T12 |
92 |
|
T2 |
21047 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2663170 |
1 |
|
|
T1 |
1342 |
|
T12 |
36 |
|
T2 |
8919 |
| auto[1] |
auto[0] |
auto[1] |
392414 |
1 |
|
|
T1 |
195 |
|
T12 |
2 |
|
T2 |
1397 |
| auto[1] |
auto[1] |
auto[0] |
2707164 |
1 |
|
|
T1 |
2376 |
|
T12 |
50 |
|
T2 |
9304 |
| auto[1] |
auto[1] |
auto[1] |
401430 |
1 |
|
|
T1 |
386 |
|
T12 |
4 |
|
T2 |
1427 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |