Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8269814 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4991 |
| auto[1] |
6171223 |
1 |
|
|
T1 |
3618 |
|
T12 |
101 |
|
T2 |
22496 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13644061 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8316 |
| auto[1] |
796976 |
1 |
|
|
T1 |
293 |
|
T12 |
6 |
|
T2 |
2826 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8257112 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6240 |
| auto[1] |
6183925 |
1 |
|
|
T1 |
2369 |
|
T12 |
114 |
|
T2 |
21805 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2698447 |
1 |
|
|
T1 |
973 |
|
T12 |
43 |
|
T2 |
8245 |
| auto[1] |
auto[0] |
auto[1] |
398083 |
1 |
|
|
T1 |
137 |
|
T12 |
3 |
|
T2 |
1197 |
| auto[1] |
auto[1] |
auto[0] |
2688502 |
1 |
|
|
T1 |
1103 |
|
T12 |
65 |
|
T2 |
10734 |
| auto[1] |
auto[1] |
auto[1] |
398893 |
1 |
|
|
T1 |
156 |
|
T12 |
3 |
|
T2 |
1629 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |