Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8252573 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4780 |
| auto[1] |
6188464 |
1 |
|
|
T1 |
3829 |
|
T12 |
87 |
|
T2 |
21529 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11860349 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
7175 |
| auto[1] |
2580688 |
1 |
|
|
T1 |
1434 |
|
T12 |
35 |
|
T2 |
7298 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8246122 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6118 |
| auto[1] |
6194915 |
1 |
|
|
T1 |
2491 |
|
T12 |
85 |
|
T2 |
19334 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1808433 |
1 |
|
|
T1 |
546 |
|
T12 |
35 |
|
T2 |
5476 |
| auto[1] |
auto[0] |
auto[1] |
1293721 |
1 |
|
|
T1 |
723 |
|
T12 |
22 |
|
T2 |
3115 |
| auto[1] |
auto[1] |
auto[0] |
1805794 |
1 |
|
|
T1 |
511 |
|
T12 |
15 |
|
T2 |
6560 |
| auto[1] |
auto[1] |
auto[1] |
1286967 |
1 |
|
|
T1 |
711 |
|
T12 |
13 |
|
T2 |
4183 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |