Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8233147 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6280 |
| auto[1] |
6207890 |
1 |
|
|
T1 |
2329 |
|
T12 |
88 |
|
T2 |
21886 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11859574 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6973 |
| auto[1] |
2581463 |
1 |
|
|
T1 |
1636 |
|
T12 |
74 |
|
T2 |
7865 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8253603 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6031 |
| auto[1] |
6187434 |
1 |
|
|
T1 |
2578 |
|
T12 |
123 |
|
T2 |
20390 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1800491 |
1 |
|
|
T1 |
448 |
|
T12 |
27 |
|
T2 |
5735 |
| auto[1] |
auto[0] |
auto[1] |
1292081 |
1 |
|
|
T1 |
811 |
|
T12 |
49 |
|
T2 |
3699 |
| auto[1] |
auto[1] |
auto[0] |
1805480 |
1 |
|
|
T1 |
494 |
|
T12 |
22 |
|
T2 |
6790 |
| auto[1] |
auto[1] |
auto[1] |
1289382 |
1 |
|
|
T1 |
825 |
|
T12 |
25 |
|
T2 |
4166 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |