Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8217287 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6221 |
| auto[1] |
6223750 |
1 |
|
|
T1 |
2388 |
|
T12 |
99 |
|
T2 |
19929 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11859086 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6058 |
| auto[1] |
2581951 |
1 |
|
|
T1 |
2551 |
|
T12 |
28 |
|
T2 |
7876 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8251889 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4805 |
| auto[1] |
6189148 |
1 |
|
|
T1 |
3804 |
|
T12 |
65 |
|
T2 |
20322 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1793173 |
1 |
|
|
T1 |
803 |
|
T12 |
7 |
|
T2 |
6585 |
| auto[1] |
auto[0] |
auto[1] |
1285900 |
1 |
|
|
T1 |
1758 |
|
T12 |
18 |
|
T2 |
4128 |
| auto[1] |
auto[1] |
auto[0] |
1814024 |
1 |
|
|
T1 |
450 |
|
T12 |
30 |
|
T2 |
5861 |
| auto[1] |
auto[1] |
auto[1] |
1296051 |
1 |
|
|
T1 |
793 |
|
T12 |
10 |
|
T2 |
3748 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |