Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8292624 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6438 |
| auto[1] |
6148413 |
1 |
|
|
T1 |
2171 |
|
T12 |
100 |
|
T2 |
19442 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11875909 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
7429 |
| auto[1] |
2565128 |
1 |
|
|
T1 |
1180 |
|
T12 |
71 |
|
T2 |
8431 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8291052 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6516 |
| auto[1] |
6149985 |
1 |
|
|
T1 |
2093 |
|
T12 |
135 |
|
T2 |
21232 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1798353 |
1 |
|
|
T1 |
457 |
|
T12 |
34 |
|
T2 |
6890 |
| auto[1] |
auto[0] |
auto[1] |
1288658 |
1 |
|
|
T1 |
567 |
|
T12 |
30 |
|
T2 |
4508 |
| auto[1] |
auto[1] |
auto[0] |
1786504 |
1 |
|
|
T1 |
456 |
|
T12 |
30 |
|
T2 |
5911 |
| auto[1] |
auto[1] |
auto[1] |
1276470 |
1 |
|
|
T1 |
613 |
|
T12 |
41 |
|
T2 |
3923 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |