Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8235985 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6278 |
| auto[1] |
6205052 |
1 |
|
|
T1 |
2331 |
|
T12 |
125 |
|
T2 |
21772 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11885675 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6090 |
| auto[1] |
2555362 |
1 |
|
|
T1 |
2519 |
|
T12 |
62 |
|
T2 |
8066 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8319187 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4511 |
| auto[1] |
6121850 |
1 |
|
|
T1 |
4098 |
|
T12 |
100 |
|
T2 |
20736 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1781399 |
1 |
|
|
T1 |
1020 |
|
T12 |
20 |
|
T2 |
5769 |
| auto[1] |
auto[0] |
auto[1] |
1277700 |
1 |
|
|
T1 |
1744 |
|
T12 |
20 |
|
T2 |
3808 |
| auto[1] |
auto[1] |
auto[0] |
1785089 |
1 |
|
|
T1 |
559 |
|
T12 |
18 |
|
T2 |
6901 |
| auto[1] |
auto[1] |
auto[1] |
1277662 |
1 |
|
|
T1 |
775 |
|
T12 |
42 |
|
T2 |
4258 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |