Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8309487 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6778 |
| auto[1] |
6131550 |
1 |
|
|
T1 |
1831 |
|
T12 |
107 |
|
T2 |
21692 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11856618 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6116 |
| auto[1] |
2584419 |
1 |
|
|
T1 |
2493 |
|
T12 |
52 |
|
T2 |
7541 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8240832 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4900 |
| auto[1] |
6200205 |
1 |
|
|
T1 |
3709 |
|
T12 |
113 |
|
T2 |
19149 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1814164 |
1 |
|
|
T1 |
941 |
|
T12 |
24 |
|
T2 |
5592 |
| auto[1] |
auto[0] |
auto[1] |
1302634 |
1 |
|
|
T1 |
1911 |
|
T12 |
23 |
|
T2 |
3822 |
| auto[1] |
auto[1] |
auto[0] |
1801622 |
1 |
|
|
T1 |
275 |
|
T12 |
37 |
|
T2 |
6016 |
| auto[1] |
auto[1] |
auto[1] |
1281785 |
1 |
|
|
T1 |
582 |
|
T12 |
29 |
|
T2 |
3719 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |