Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8266820 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4977 |
| auto[1] |
6174217 |
1 |
|
|
T1 |
3632 |
|
T12 |
77 |
|
T2 |
22177 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11844033 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
7169 |
| auto[1] |
2597004 |
1 |
|
|
T1 |
1440 |
|
T12 |
55 |
|
T2 |
8090 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8214391 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6317 |
| auto[1] |
6226646 |
1 |
|
|
T1 |
2292 |
|
T12 |
106 |
|
T2 |
20690 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1824888 |
1 |
|
|
T1 |
411 |
|
T12 |
36 |
|
T2 |
6134 |
| auto[1] |
auto[0] |
auto[1] |
1310907 |
1 |
|
|
T1 |
684 |
|
T12 |
37 |
|
T2 |
3963 |
| auto[1] |
auto[1] |
auto[0] |
1804754 |
1 |
|
|
T1 |
441 |
|
T12 |
15 |
|
T2 |
6466 |
| auto[1] |
auto[1] |
auto[1] |
1286097 |
1 |
|
|
T1 |
756 |
|
T12 |
18 |
|
T2 |
4127 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |