Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8234755 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6637 |
| auto[1] |
6206282 |
1 |
|
|
T1 |
1972 |
|
T12 |
96 |
|
T2 |
21662 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11848852 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6081 |
| auto[1] |
2592185 |
1 |
|
|
T1 |
2528 |
|
T12 |
32 |
|
T2 |
8464 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8215167 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4797 |
| auto[1] |
6225870 |
1 |
|
|
T1 |
3812 |
|
T12 |
84 |
|
T2 |
21730 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1822277 |
1 |
|
|
T1 |
899 |
|
T12 |
23 |
|
T2 |
7077 |
| auto[1] |
auto[0] |
auto[1] |
1298102 |
1 |
|
|
T1 |
1806 |
|
T12 |
12 |
|
T2 |
4198 |
| auto[1] |
auto[1] |
auto[0] |
1811408 |
1 |
|
|
T1 |
385 |
|
T12 |
29 |
|
T2 |
6189 |
| auto[1] |
auto[1] |
auto[1] |
1294083 |
1 |
|
|
T1 |
722 |
|
T12 |
20 |
|
T2 |
4266 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |