Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8229327 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4973 |
| auto[1] |
6211710 |
1 |
|
|
T1 |
3636 |
|
T12 |
108 |
|
T2 |
20247 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11868447 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
7269 |
| auto[1] |
2572590 |
1 |
|
|
T1 |
1340 |
|
T12 |
60 |
|
T2 |
7728 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8259063 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6262 |
| auto[1] |
6181974 |
1 |
|
|
T1 |
2347 |
|
T12 |
99 |
|
T2 |
19859 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1795371 |
1 |
|
|
T1 |
496 |
|
T12 |
12 |
|
T2 |
6233 |
| auto[1] |
auto[0] |
auto[1] |
1283491 |
1 |
|
|
T1 |
704 |
|
T12 |
15 |
|
T2 |
3877 |
| auto[1] |
auto[1] |
auto[0] |
1814013 |
1 |
|
|
T1 |
511 |
|
T12 |
27 |
|
T2 |
5898 |
| auto[1] |
auto[1] |
auto[1] |
1289099 |
1 |
|
|
T1 |
636 |
|
T12 |
45 |
|
T2 |
3851 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |