Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8256844 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4742 |
| auto[1] |
6184193 |
1 |
|
|
T1 |
3867 |
|
T12 |
134 |
|
T2 |
21442 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11860133 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6271 |
| auto[1] |
2580904 |
1 |
|
|
T1 |
2338 |
|
T12 |
57 |
|
T2 |
8272 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8238815 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
5022 |
| auto[1] |
6202222 |
1 |
|
|
T1 |
3587 |
|
T12 |
87 |
|
T2 |
21685 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1805050 |
1 |
|
|
T1 |
402 |
|
T12 |
2 |
|
T2 |
6776 |
| auto[1] |
auto[0] |
auto[1] |
1292451 |
1 |
|
|
T1 |
526 |
|
T12 |
20 |
|
T2 |
3983 |
| auto[1] |
auto[1] |
auto[0] |
1816268 |
1 |
|
|
T1 |
847 |
|
T12 |
28 |
|
T2 |
6637 |
| auto[1] |
auto[1] |
auto[1] |
1288453 |
1 |
|
|
T1 |
1812 |
|
T12 |
37 |
|
T2 |
4289 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |