Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8230561 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6616 |
| auto[1] |
6210476 |
1 |
|
|
T1 |
1993 |
|
T12 |
67 |
|
T2 |
21012 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11870405 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
7188 |
| auto[1] |
2570632 |
1 |
|
|
T1 |
1421 |
|
T12 |
60 |
|
T2 |
9000 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8265811 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6071 |
| auto[1] |
6175226 |
1 |
|
|
T1 |
2538 |
|
T12 |
107 |
|
T2 |
23080 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1784589 |
1 |
|
|
T1 |
630 |
|
T12 |
23 |
|
T2 |
7153 |
| auto[1] |
auto[0] |
auto[1] |
1280117 |
1 |
|
|
T1 |
800 |
|
T12 |
34 |
|
T2 |
4646 |
| auto[1] |
auto[1] |
auto[0] |
1820005 |
1 |
|
|
T1 |
487 |
|
T12 |
24 |
|
T2 |
6927 |
| auto[1] |
auto[1] |
auto[1] |
1290515 |
1 |
|
|
T1 |
621 |
|
T12 |
26 |
|
T2 |
4354 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |