Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8278731 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6622 |
| auto[1] |
6162306 |
1 |
|
|
T1 |
1987 |
|
T12 |
123 |
|
T2 |
19540 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11863179 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6290 |
| auto[1] |
2577858 |
1 |
|
|
T1 |
2319 |
|
T12 |
31 |
|
T2 |
8746 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8255210 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
5075 |
| auto[1] |
6185827 |
1 |
|
|
T1 |
3534 |
|
T12 |
99 |
|
T2 |
21581 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1817276 |
1 |
|
|
T1 |
798 |
|
T12 |
20 |
|
T2 |
7190 |
| auto[1] |
auto[0] |
auto[1] |
1291633 |
1 |
|
|
T1 |
1679 |
|
T12 |
8 |
|
T2 |
4847 |
| auto[1] |
auto[1] |
auto[0] |
1790693 |
1 |
|
|
T1 |
417 |
|
T12 |
48 |
|
T2 |
5645 |
| auto[1] |
auto[1] |
auto[1] |
1286225 |
1 |
|
|
T1 |
640 |
|
T12 |
23 |
|
T2 |
3899 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |