Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8247897 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6627 |
| auto[1] |
6193140 |
1 |
|
|
T1 |
1982 |
|
T12 |
63 |
|
T2 |
20524 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11867857 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
7355 |
| auto[1] |
2573180 |
1 |
|
|
T1 |
1254 |
|
T12 |
65 |
|
T2 |
8559 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8248092 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6458 |
| auto[1] |
6192945 |
1 |
|
|
T1 |
2151 |
|
T12 |
133 |
|
T2 |
21753 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1800566 |
1 |
|
|
T1 |
517 |
|
T12 |
56 |
|
T2 |
6490 |
| auto[1] |
auto[0] |
auto[1] |
1282559 |
1 |
|
|
T1 |
711 |
|
T12 |
46 |
|
T2 |
4217 |
| auto[1] |
auto[1] |
auto[0] |
1819199 |
1 |
|
|
T1 |
380 |
|
T12 |
12 |
|
T2 |
6704 |
| auto[1] |
auto[1] |
auto[1] |
1290621 |
1 |
|
|
T1 |
543 |
|
T12 |
19 |
|
T2 |
4342 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |