Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8255153 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4709 |
| auto[1] |
6185884 |
1 |
|
|
T1 |
3900 |
|
T12 |
113 |
|
T2 |
21017 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11866817 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6252 |
| auto[1] |
2574220 |
1 |
|
|
T1 |
2357 |
|
T12 |
46 |
|
T2 |
7988 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8281340 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4909 |
| auto[1] |
6159697 |
1 |
|
|
T1 |
3700 |
|
T12 |
117 |
|
T2 |
21376 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1786328 |
1 |
|
|
T1 |
451 |
|
T12 |
33 |
|
T2 |
6416 |
| auto[1] |
auto[0] |
auto[1] |
1282927 |
1 |
|
|
T1 |
588 |
|
T12 |
21 |
|
T2 |
4065 |
| auto[1] |
auto[1] |
auto[0] |
1799149 |
1 |
|
|
T1 |
892 |
|
T12 |
38 |
|
T2 |
6972 |
| auto[1] |
auto[1] |
auto[1] |
1291293 |
1 |
|
|
T1 |
1769 |
|
T12 |
25 |
|
T2 |
3923 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |