Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8246687 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6361 |
| auto[1] |
6194350 |
1 |
|
|
T1 |
2248 |
|
T12 |
73 |
|
T2 |
21562 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13641085 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8396 |
| auto[1] |
799952 |
1 |
|
|
T1 |
213 |
|
T12 |
6 |
|
T2 |
2609 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8231347 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6697 |
| auto[1] |
6209690 |
1 |
|
|
T1 |
1912 |
|
T12 |
100 |
|
T2 |
20667 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2705516 |
1 |
|
|
T1 |
904 |
|
T12 |
67 |
|
T2 |
8504 |
| auto[1] |
auto[0] |
auto[1] |
401045 |
1 |
|
|
T1 |
122 |
|
T12 |
5 |
|
T2 |
1261 |
| auto[1] |
auto[1] |
auto[0] |
2704222 |
1 |
|
|
T1 |
795 |
|
T12 |
27 |
|
T2 |
9554 |
| auto[1] |
auto[1] |
auto[1] |
398907 |
1 |
|
|
T1 |
91 |
|
T12 |
1 |
|
T2 |
1348 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |