Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8268265 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4987 |
| auto[1] |
6172772 |
1 |
|
|
T1 |
3622 |
|
T12 |
91 |
|
T2 |
19982 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11865574 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
7204 |
| auto[1] |
2575463 |
1 |
|
|
T1 |
1405 |
|
T12 |
48 |
|
T2 |
8258 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8275845 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6177 |
| auto[1] |
6165192 |
1 |
|
|
T1 |
2432 |
|
T12 |
111 |
|
T2 |
21244 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1800381 |
1 |
|
|
T1 |
496 |
|
T12 |
38 |
|
T2 |
7049 |
| auto[1] |
auto[0] |
auto[1] |
1293293 |
1 |
|
|
T1 |
757 |
|
T12 |
28 |
|
T2 |
4561 |
| auto[1] |
auto[1] |
auto[0] |
1789348 |
1 |
|
|
T1 |
531 |
|
T12 |
25 |
|
T2 |
5937 |
| auto[1] |
auto[1] |
auto[1] |
1282170 |
1 |
|
|
T1 |
648 |
|
T12 |
20 |
|
T2 |
3697 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |