Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8277650 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6498 |
| auto[1] |
6163387 |
1 |
|
|
T1 |
2111 |
|
T12 |
106 |
|
T2 |
21944 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11877368 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
7278 |
| auto[1] |
2563669 |
1 |
|
|
T1 |
1331 |
|
T12 |
49 |
|
T2 |
7132 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8293651 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6347 |
| auto[1] |
6147386 |
1 |
|
|
T1 |
2262 |
|
T12 |
125 |
|
T2 |
18222 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1811492 |
1 |
|
|
T1 |
434 |
|
T12 |
45 |
|
T2 |
5963 |
| auto[1] |
auto[0] |
auto[1] |
1294205 |
1 |
|
|
T1 |
732 |
|
T12 |
17 |
|
T2 |
3666 |
| auto[1] |
auto[1] |
auto[0] |
1772225 |
1 |
|
|
T1 |
497 |
|
T12 |
31 |
|
T2 |
5127 |
| auto[1] |
auto[1] |
auto[1] |
1269464 |
1 |
|
|
T1 |
599 |
|
T12 |
32 |
|
T2 |
3466 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |