Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8253724 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4924 |
| auto[1] |
6187313 |
1 |
|
|
T1 |
3685 |
|
T12 |
152 |
|
T2 |
19775 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11880811 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
7361 |
| auto[1] |
2560226 |
1 |
|
|
T1 |
1248 |
|
T12 |
63 |
|
T2 |
8341 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8295242 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6590 |
| auto[1] |
6145795 |
1 |
|
|
T1 |
2019 |
|
T12 |
123 |
|
T2 |
20799 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1803987 |
1 |
|
|
T1 |
377 |
|
T12 |
7 |
|
T2 |
6768 |
| auto[1] |
auto[0] |
auto[1] |
1286377 |
1 |
|
|
T1 |
623 |
|
T12 |
31 |
|
T2 |
4458 |
| auto[1] |
auto[1] |
auto[0] |
1781582 |
1 |
|
|
T1 |
394 |
|
T12 |
53 |
|
T2 |
5690 |
| auto[1] |
auto[1] |
auto[1] |
1273849 |
1 |
|
|
T1 |
625 |
|
T12 |
32 |
|
T2 |
3883 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |