Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8214955 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4822 |
| auto[1] |
6226082 |
1 |
|
|
T1 |
3787 |
|
T12 |
112 |
|
T2 |
19699 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13644437 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8355 |
| auto[1] |
796600 |
1 |
|
|
T1 |
254 |
|
T12 |
3 |
|
T2 |
3001 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8248909 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6454 |
| auto[1] |
6192128 |
1 |
|
|
T1 |
2155 |
|
T12 |
82 |
|
T2 |
22446 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2689388 |
1 |
|
|
T1 |
885 |
|
T12 |
36 |
|
T2 |
10362 |
| auto[1] |
auto[0] |
auto[1] |
397239 |
1 |
|
|
T1 |
126 |
|
T12 |
2 |
|
T2 |
1579 |
| auto[1] |
auto[1] |
auto[0] |
2706140 |
1 |
|
|
T1 |
1016 |
|
T12 |
43 |
|
T2 |
9083 |
| auto[1] |
auto[1] |
auto[1] |
399361 |
1 |
|
|
T1 |
128 |
|
T12 |
1 |
|
T2 |
1422 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |