Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8258940 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4696 |
| auto[1] |
6182097 |
1 |
|
|
T1 |
3913 |
|
T12 |
104 |
|
T2 |
19886 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13642872 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8130 |
| auto[1] |
798165 |
1 |
|
|
T1 |
479 |
|
T12 |
4 |
|
T2 |
2529 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8241856 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
5240 |
| auto[1] |
6199181 |
1 |
|
|
T1 |
3369 |
|
T12 |
60 |
|
T2 |
19691 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2701222 |
1 |
|
|
T1 |
767 |
|
T12 |
30 |
|
T2 |
9226 |
| auto[1] |
auto[0] |
auto[1] |
398999 |
1 |
|
|
T1 |
103 |
|
T12 |
1 |
|
T2 |
1386 |
| auto[1] |
auto[1] |
auto[0] |
2699794 |
1 |
|
|
T1 |
2123 |
|
T12 |
26 |
|
T2 |
7936 |
| auto[1] |
auto[1] |
auto[1] |
399166 |
1 |
|
|
T1 |
376 |
|
T12 |
3 |
|
T2 |
1143 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |