Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8247026 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6558 |
| auto[1] |
6194011 |
1 |
|
|
T1 |
2051 |
|
T12 |
97 |
|
T2 |
19657 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13639509 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8283 |
| auto[1] |
801528 |
1 |
|
|
T1 |
326 |
|
T12 |
8 |
|
T2 |
2800 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8229888 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6227 |
| auto[1] |
6211149 |
1 |
|
|
T1 |
2382 |
|
T12 |
99 |
|
T2 |
21582 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2696471 |
1 |
|
|
T1 |
1083 |
|
T12 |
44 |
|
T2 |
9311 |
| auto[1] |
auto[0] |
auto[1] |
399664 |
1 |
|
|
T1 |
159 |
|
T12 |
3 |
|
T2 |
1428 |
| auto[1] |
auto[1] |
auto[0] |
2713150 |
1 |
|
|
T1 |
973 |
|
T12 |
47 |
|
T2 |
9471 |
| auto[1] |
auto[1] |
auto[1] |
401864 |
1 |
|
|
T1 |
167 |
|
T12 |
5 |
|
T2 |
1372 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |