Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8238112 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4924 |
| auto[1] |
6202925 |
1 |
|
|
T1 |
3685 |
|
T12 |
73 |
|
T2 |
21362 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13642457 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8268 |
| auto[1] |
798580 |
1 |
|
|
T1 |
341 |
|
T12 |
7 |
|
T2 |
2563 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8238342 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6152 |
| auto[1] |
6202695 |
1 |
|
|
T1 |
2457 |
|
T12 |
100 |
|
T2 |
19750 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2697281 |
1 |
|
|
T1 |
1110 |
|
T12 |
55 |
|
T2 |
8584 |
| auto[1] |
auto[0] |
auto[1] |
397376 |
1 |
|
|
T1 |
175 |
|
T12 |
6 |
|
T2 |
1215 |
| auto[1] |
auto[1] |
auto[0] |
2706834 |
1 |
|
|
T1 |
1006 |
|
T12 |
38 |
|
T2 |
8603 |
| auto[1] |
auto[1] |
auto[1] |
401204 |
1 |
|
|
T1 |
166 |
|
T12 |
1 |
|
T2 |
1348 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |