Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8270650 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6659 |
| auto[1] |
6170387 |
1 |
|
|
T1 |
1950 |
|
T12 |
70 |
|
T2 |
21645 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13647024 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8035 |
| auto[1] |
794013 |
1 |
|
|
T1 |
574 |
|
T12 |
8 |
|
T2 |
2677 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8275333 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4539 |
| auto[1] |
6165704 |
1 |
|
|
T1 |
4070 |
|
T12 |
127 |
|
T2 |
20576 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2706219 |
1 |
|
|
T1 |
2484 |
|
T12 |
56 |
|
T2 |
8628 |
| auto[1] |
auto[0] |
auto[1] |
400934 |
1 |
|
|
T1 |
446 |
|
T12 |
5 |
|
T2 |
1214 |
| auto[1] |
auto[1] |
auto[0] |
2665472 |
1 |
|
|
T1 |
1012 |
|
T12 |
63 |
|
T2 |
9271 |
| auto[1] |
auto[1] |
auto[1] |
393079 |
1 |
|
|
T1 |
128 |
|
T12 |
3 |
|
T2 |
1463 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |