Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8244444 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
6299 |
| auto[1] |
6196593 |
1 |
|
|
T1 |
2310 |
|
T12 |
133 |
|
T2 |
20300 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13646089 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
8011 |
| auto[1] |
794948 |
1 |
|
|
T1 |
598 |
|
T12 |
7 |
|
T2 |
2835 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8269390 |
1 |
|
|
T24 |
349 |
|
T25 |
1 |
|
T1 |
4687 |
| auto[1] |
6171647 |
1 |
|
|
T1 |
3922 |
|
T12 |
104 |
|
T2 |
21000 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2689775 |
1 |
|
|
T1 |
2218 |
|
T12 |
39 |
|
T2 |
9360 |
| auto[1] |
auto[0] |
auto[1] |
397703 |
1 |
|
|
T1 |
422 |
|
T12 |
3 |
|
T2 |
1503 |
| auto[1] |
auto[1] |
auto[0] |
2686924 |
1 |
|
|
T1 |
1106 |
|
T12 |
58 |
|
T2 |
8805 |
| auto[1] |
auto[1] |
auto[1] |
397245 |
1 |
|
|
T1 |
176 |
|
T12 |
4 |
|
T2 |
1332 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |