Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 943
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T765 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.269750603 Jul 28 05:11:23 PM PDT 24 Jul 28 05:11:24 PM PDT 24 222297291 ps
T766 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2015665 Jul 28 05:11:37 PM PDT 24 Jul 28 05:11:40 PM PDT 24 325277463 ps
T767 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1378139898 Jul 28 05:11:18 PM PDT 24 Jul 28 05:11:25 PM PDT 24 132217638 ps
T768 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2127397431 Jul 28 05:11:26 PM PDT 24 Jul 28 05:11:27 PM PDT 24 24304828 ps
T769 /workspace/coverage/cover_reg_top/13.gpio_intr_test.3149296049 Jul 28 05:11:57 PM PDT 24 Jul 28 05:11:58 PM PDT 24 14862983 ps
T770 /workspace/coverage/cover_reg_top/32.gpio_intr_test.3313435301 Jul 28 05:11:35 PM PDT 24 Jul 28 05:11:35 PM PDT 24 31979876 ps
T771 /workspace/coverage/cover_reg_top/9.gpio_intr_test.702940194 Jul 28 05:11:34 PM PDT 24 Jul 28 05:11:34 PM PDT 24 16255758 ps
T772 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1309270078 Jul 28 05:11:30 PM PDT 24 Jul 28 05:11:31 PM PDT 24 152398405 ps
T773 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.283663638 Jul 28 05:11:25 PM PDT 24 Jul 28 05:11:26 PM PDT 24 11775984 ps
T774 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.887788014 Jul 28 05:11:13 PM PDT 24 Jul 28 05:11:15 PM PDT 24 44217607 ps
T775 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1043763122 Jul 28 05:11:32 PM PDT 24 Jul 28 05:11:38 PM PDT 24 65045781 ps
T67 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3519839885 Jul 28 05:11:27 PM PDT 24 Jul 28 05:11:28 PM PDT 24 14195874 ps
T776 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3684995244 Jul 28 05:11:37 PM PDT 24 Jul 28 05:11:38 PM PDT 24 25348988 ps
T68 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2265867301 Jul 28 05:11:18 PM PDT 24 Jul 28 05:11:19 PM PDT 24 12574226 ps
T777 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1674219096 Jul 28 05:11:24 PM PDT 24 Jul 28 05:11:25 PM PDT 24 117792812 ps
T778 /workspace/coverage/cover_reg_top/11.gpio_intr_test.559947568 Jul 28 05:11:23 PM PDT 24 Jul 28 05:11:24 PM PDT 24 75182720 ps
T779 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2641880372 Jul 28 05:11:25 PM PDT 24 Jul 28 05:11:27 PM PDT 24 217660748 ps
T780 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.778672163 Jul 28 05:11:20 PM PDT 24 Jul 28 05:11:20 PM PDT 24 17172658 ps
T41 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1508603538 Jul 28 05:11:25 PM PDT 24 Jul 28 05:11:26 PM PDT 24 149595651 ps
T781 /workspace/coverage/cover_reg_top/25.gpio_intr_test.1280014156 Jul 28 05:11:42 PM PDT 24 Jul 28 05:11:43 PM PDT 24 14377524 ps
T782 /workspace/coverage/cover_reg_top/43.gpio_intr_test.2059397325 Jul 28 05:11:36 PM PDT 24 Jul 28 05:11:37 PM PDT 24 17077730 ps
T783 /workspace/coverage/cover_reg_top/30.gpio_intr_test.3677136559 Jul 28 05:12:08 PM PDT 24 Jul 28 05:12:09 PM PDT 24 17508701 ps
T784 /workspace/coverage/cover_reg_top/27.gpio_intr_test.3720726523 Jul 28 05:11:37 PM PDT 24 Jul 28 05:11:37 PM PDT 24 58123841 ps
T785 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3982757613 Jul 28 05:11:29 PM PDT 24 Jul 28 05:11:30 PM PDT 24 77158020 ps
T786 /workspace/coverage/cover_reg_top/22.gpio_intr_test.1326090900 Jul 28 05:11:41 PM PDT 24 Jul 28 05:11:42 PM PDT 24 78789089 ps
T787 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.228539040 Jul 28 05:11:29 PM PDT 24 Jul 28 05:11:31 PM PDT 24 69222807 ps
T788 /workspace/coverage/cover_reg_top/17.gpio_intr_test.3676446300 Jul 28 05:11:41 PM PDT 24 Jul 28 05:11:41 PM PDT 24 14962119 ps
T69 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3114671828 Jul 28 05:11:20 PM PDT 24 Jul 28 05:11:21 PM PDT 24 24170534 ps
T789 /workspace/coverage/cover_reg_top/40.gpio_intr_test.2061907540 Jul 28 05:11:36 PM PDT 24 Jul 28 05:11:37 PM PDT 24 127985159 ps
T94 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3618064799 Jul 28 05:11:29 PM PDT 24 Jul 28 05:11:30 PM PDT 24 652738042 ps
T790 /workspace/coverage/cover_reg_top/26.gpio_intr_test.241485405 Jul 28 05:11:45 PM PDT 24 Jul 28 05:11:46 PM PDT 24 17543178 ps
T791 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3420074616 Jul 28 05:11:31 PM PDT 24 Jul 28 05:11:31 PM PDT 24 22749781 ps
T792 /workspace/coverage/cover_reg_top/47.gpio_intr_test.4245170994 Jul 28 05:11:41 PM PDT 24 Jul 28 05:11:42 PM PDT 24 13581231 ps
T793 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3610796468 Jul 28 05:11:37 PM PDT 24 Jul 28 05:11:38 PM PDT 24 26272140 ps
T794 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3507673838 Jul 28 05:11:18 PM PDT 24 Jul 28 05:11:19 PM PDT 24 52581697 ps
T37 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1684024433 Jul 28 05:11:28 PM PDT 24 Jul 28 05:11:30 PM PDT 24 228161881 ps
T795 /workspace/coverage/cover_reg_top/24.gpio_intr_test.3093618717 Jul 28 05:11:38 PM PDT 24 Jul 28 05:11:39 PM PDT 24 45711222 ps
T796 /workspace/coverage/cover_reg_top/8.gpio_intr_test.3426116313 Jul 28 05:11:33 PM PDT 24 Jul 28 05:11:33 PM PDT 24 26404739 ps
T797 /workspace/coverage/cover_reg_top/7.gpio_intr_test.1263564106 Jul 28 05:11:22 PM PDT 24 Jul 28 05:11:22 PM PDT 24 13528159 ps
T798 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2889151195 Jul 28 05:11:42 PM PDT 24 Jul 28 05:11:43 PM PDT 24 172145424 ps
T799 /workspace/coverage/cover_reg_top/48.gpio_intr_test.2188344524 Jul 28 05:11:41 PM PDT 24 Jul 28 05:11:42 PM PDT 24 14384658 ps
T800 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1942601404 Jul 28 05:11:29 PM PDT 24 Jul 28 05:11:30 PM PDT 24 35324285 ps
T801 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3004644607 Jul 28 05:11:44 PM PDT 24 Jul 28 05:11:45 PM PDT 24 21345118 ps
T802 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.378301968 Jul 28 05:11:31 PM PDT 24 Jul 28 05:11:32 PM PDT 24 30588777 ps
T803 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.396441062 Jul 28 05:11:27 PM PDT 24 Jul 28 05:11:28 PM PDT 24 33589594 ps
T804 /workspace/coverage/cover_reg_top/49.gpio_intr_test.2029901106 Jul 28 05:11:37 PM PDT 24 Jul 28 05:11:38 PM PDT 24 25107188 ps
T805 /workspace/coverage/cover_reg_top/45.gpio_intr_test.96649855 Jul 28 05:11:33 PM PDT 24 Jul 28 05:11:33 PM PDT 24 47812456 ps
T70 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3356757572 Jul 28 05:11:21 PM PDT 24 Jul 28 05:11:22 PM PDT 24 18663326 ps
T806 /workspace/coverage/cover_reg_top/5.gpio_intr_test.3811523666 Jul 28 05:11:28 PM PDT 24 Jul 28 05:11:28 PM PDT 24 40967138 ps
T807 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3650737339 Jul 28 05:11:48 PM PDT 24 Jul 28 05:11:49 PM PDT 24 42036016 ps
T808 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2374810233 Jul 28 05:11:26 PM PDT 24 Jul 28 05:11:27 PM PDT 24 446934812 ps
T809 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.516320059 Jul 28 05:11:43 PM PDT 24 Jul 28 05:11:44 PM PDT 24 152405440 ps
T810 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3234569085 Jul 28 05:11:31 PM PDT 24 Jul 28 05:11:32 PM PDT 24 33230017 ps
T811 /workspace/coverage/cover_reg_top/34.gpio_intr_test.1840199239 Jul 28 05:11:37 PM PDT 24 Jul 28 05:11:38 PM PDT 24 52034206 ps
T812 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1275285194 Jul 28 05:11:31 PM PDT 24 Jul 28 05:11:32 PM PDT 24 32713312 ps
T813 /workspace/coverage/cover_reg_top/6.gpio_intr_test.2350212187 Jul 28 05:11:22 PM PDT 24 Jul 28 05:11:23 PM PDT 24 57736347 ps
T814 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.562937864 Jul 28 05:11:19 PM PDT 24 Jul 28 05:11:21 PM PDT 24 111754346 ps
T815 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1754046131 Jul 28 05:11:45 PM PDT 24 Jul 28 05:11:46 PM PDT 24 35956997 ps
T816 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.4028194197 Jul 28 05:11:32 PM PDT 24 Jul 28 05:11:32 PM PDT 24 95869368 ps
T817 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2865919858 Jul 28 05:11:20 PM PDT 24 Jul 28 05:11:24 PM PDT 24 156471905 ps
T818 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.52877968 Jul 28 05:11:20 PM PDT 24 Jul 28 05:11:20 PM PDT 24 20286491 ps
T819 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1831781600 Jul 28 05:11:36 PM PDT 24 Jul 28 05:11:42 PM PDT 24 132458435 ps
T71 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.376534070 Jul 28 05:11:34 PM PDT 24 Jul 28 05:11:35 PM PDT 24 56299195 ps
T820 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1641284469 Jul 28 05:11:22 PM PDT 24 Jul 28 05:11:23 PM PDT 24 23912844 ps
T72 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.911621880 Jul 28 05:11:15 PM PDT 24 Jul 28 05:11:16 PM PDT 24 14268618 ps
T821 /workspace/coverage/cover_reg_top/14.gpio_intr_test.3097793899 Jul 28 05:11:26 PM PDT 24 Jul 28 05:11:26 PM PDT 24 76387319 ps
T822 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.847650721 Jul 28 05:11:36 PM PDT 24 Jul 28 05:11:37 PM PDT 24 368833113 ps
T823 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.374268563 Jul 28 05:11:13 PM PDT 24 Jul 28 05:11:14 PM PDT 24 58301130 ps
T73 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3506162431 Jul 28 05:11:31 PM PDT 24 Jul 28 05:11:32 PM PDT 24 15093773 ps
T824 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.4276638099 Jul 28 05:11:24 PM PDT 24 Jul 28 05:11:27 PM PDT 24 1144256216 ps
T825 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.124859385 Jul 28 05:11:40 PM PDT 24 Jul 28 05:11:46 PM PDT 24 96719983 ps
T75 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.635149470 Jul 28 05:11:24 PM PDT 24 Jul 28 05:11:27 PM PDT 24 79256070 ps
T826 /workspace/coverage/cover_reg_top/31.gpio_intr_test.1095315725 Jul 28 05:11:39 PM PDT 24 Jul 28 05:11:39 PM PDT 24 14358948 ps
T78 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1444346546 Jul 28 05:11:31 PM PDT 24 Jul 28 05:11:31 PM PDT 24 39589865 ps
T77 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3939720982 Jul 28 05:11:23 PM PDT 24 Jul 28 05:11:24 PM PDT 24 11046003 ps
T827 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1547763700 Jul 28 05:11:13 PM PDT 24 Jul 28 05:11:14 PM PDT 24 45449128 ps
T828 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.4047536090 Jul 28 05:11:28 PM PDT 24 Jul 28 05:11:29 PM PDT 24 225880669 ps
T76 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4148360260 Jul 28 05:11:28 PM PDT 24 Jul 28 05:11:29 PM PDT 24 17031082 ps
T829 /workspace/coverage/cover_reg_top/33.gpio_intr_test.2746541969 Jul 28 05:11:47 PM PDT 24 Jul 28 05:11:48 PM PDT 24 16946835 ps
T830 /workspace/coverage/cover_reg_top/23.gpio_intr_test.2982256920 Jul 28 05:11:31 PM PDT 24 Jul 28 05:11:32 PM PDT 24 15753379 ps
T831 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.4084121278 Jul 28 05:11:28 PM PDT 24 Jul 28 05:11:29 PM PDT 24 360744692 ps
T832 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2887255221 Jul 28 05:11:29 PM PDT 24 Jul 28 05:11:29 PM PDT 24 26876567 ps
T833 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.167016733 Jul 28 05:11:19 PM PDT 24 Jul 28 05:11:19 PM PDT 24 32134434 ps
T834 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.576715945 Jul 28 05:11:32 PM PDT 24 Jul 28 05:11:38 PM PDT 24 38889750 ps
T835 /workspace/coverage/cover_reg_top/38.gpio_intr_test.2172288583 Jul 28 05:11:31 PM PDT 24 Jul 28 05:11:32 PM PDT 24 14157232 ps
T836 /workspace/coverage/cover_reg_top/20.gpio_intr_test.3546715225 Jul 28 05:11:28 PM PDT 24 Jul 28 05:11:28 PM PDT 24 42684571 ps
T837 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2363833606 Jul 28 05:11:28 PM PDT 24 Jul 28 05:11:29 PM PDT 24 63736452 ps
T838 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3377082714 Jul 28 05:11:41 PM PDT 24 Jul 28 05:11:44 PM PDT 24 166780886 ps
T839 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.4173243751 Jul 28 05:11:18 PM PDT 24 Jul 28 05:11:18 PM PDT 24 42950406 ps
T840 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.868295469 Jul 28 05:11:32 PM PDT 24 Jul 28 05:11:32 PM PDT 24 74609259 ps
T841 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1959751507 Jul 28 05:11:54 PM PDT 24 Jul 28 05:11:57 PM PDT 24 271679069 ps
T842 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.4239818685 Jul 28 05:11:22 PM PDT 24 Jul 28 05:11:23 PM PDT 24 143151121 ps
T843 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2318981458 Jul 28 05:11:26 PM PDT 24 Jul 28 05:11:27 PM PDT 24 47843734 ps
T844 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.98417439 Jul 28 05:11:51 PM PDT 24 Jul 28 05:11:52 PM PDT 24 92359212 ps
T845 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3498218393 Jul 28 05:11:53 PM PDT 24 Jul 28 05:11:54 PM PDT 24 80987053 ps
T846 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2689099726 Jul 28 05:11:47 PM PDT 24 Jul 28 05:11:48 PM PDT 24 18941800 ps
T847 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3438242531 Jul 28 05:11:55 PM PDT 24 Jul 28 05:11:57 PM PDT 24 303729933 ps
T848 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4183540844 Jul 28 05:11:53 PM PDT 24 Jul 28 05:11:54 PM PDT 24 114577981 ps
T849 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2767077756 Jul 28 05:11:41 PM PDT 24 Jul 28 05:11:42 PM PDT 24 37149922 ps
T850 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3236958844 Jul 28 05:11:55 PM PDT 24 Jul 28 05:11:56 PM PDT 24 163219778 ps
T851 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3643434534 Jul 28 05:11:55 PM PDT 24 Jul 28 05:11:57 PM PDT 24 348269040 ps
T852 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.75347354 Jul 28 05:11:53 PM PDT 24 Jul 28 05:11:54 PM PDT 24 163501267 ps
T853 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.477873756 Jul 28 05:12:00 PM PDT 24 Jul 28 05:12:01 PM PDT 24 49744944 ps
T854 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1556013298 Jul 28 05:11:48 PM PDT 24 Jul 28 05:11:49 PM PDT 24 763474591 ps
T855 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.968272979 Jul 28 05:11:55 PM PDT 24 Jul 28 05:11:56 PM PDT 24 48221548 ps
T856 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2747211698 Jul 28 05:11:55 PM PDT 24 Jul 28 05:11:56 PM PDT 24 313055616 ps
T857 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.802371557 Jul 28 05:11:39 PM PDT 24 Jul 28 05:11:40 PM PDT 24 454322191 ps
T858 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2159925732 Jul 28 05:12:05 PM PDT 24 Jul 28 05:12:07 PM PDT 24 44552899 ps
T859 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2467395753 Jul 28 05:11:42 PM PDT 24 Jul 28 05:11:44 PM PDT 24 74145449 ps
T860 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3839825536 Jul 28 05:12:06 PM PDT 24 Jul 28 05:12:08 PM PDT 24 85181826 ps
T861 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3240101607 Jul 28 05:11:29 PM PDT 24 Jul 28 05:11:30 PM PDT 24 52724633 ps
T862 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.463899324 Jul 28 05:11:57 PM PDT 24 Jul 28 05:11:58 PM PDT 24 143145060 ps
T863 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.180934885 Jul 28 05:11:51 PM PDT 24 Jul 28 05:11:52 PM PDT 24 100077833 ps
T864 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2439759951 Jul 28 05:11:50 PM PDT 24 Jul 28 05:11:51 PM PDT 24 63381887 ps
T865 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3044594781 Jul 28 05:11:42 PM PDT 24 Jul 28 05:11:44 PM PDT 24 163102063 ps
T866 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1450031066 Jul 28 05:12:06 PM PDT 24 Jul 28 05:12:07 PM PDT 24 240195922 ps
T867 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1459019348 Jul 28 05:11:50 PM PDT 24 Jul 28 05:11:51 PM PDT 24 204423968 ps
T868 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1722161310 Jul 28 05:11:40 PM PDT 24 Jul 28 05:11:41 PM PDT 24 465429817 ps
T869 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2605934869 Jul 28 05:11:52 PM PDT 24 Jul 28 05:11:54 PM PDT 24 173833734 ps
T870 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1340217567 Jul 28 05:11:35 PM PDT 24 Jul 28 05:11:36 PM PDT 24 104150752 ps
T871 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2515244599 Jul 28 05:11:36 PM PDT 24 Jul 28 05:11:38 PM PDT 24 492822430 ps
T872 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2880642574 Jul 28 05:12:05 PM PDT 24 Jul 28 05:12:06 PM PDT 24 32259309 ps
T873 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4208980241 Jul 28 05:11:38 PM PDT 24 Jul 28 05:11:39 PM PDT 24 52924271 ps
T874 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2142904782 Jul 28 05:11:37 PM PDT 24 Jul 28 05:11:38 PM PDT 24 88498070 ps
T875 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3936706335 Jul 28 05:11:44 PM PDT 24 Jul 28 05:11:45 PM PDT 24 183360827 ps
T876 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1344903168 Jul 28 05:11:57 PM PDT 24 Jul 28 05:11:59 PM PDT 24 46359130 ps
T877 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3393247184 Jul 28 05:12:00 PM PDT 24 Jul 28 05:12:06 PM PDT 24 215919384 ps
T878 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3262301997 Jul 28 05:11:42 PM PDT 24 Jul 28 05:11:43 PM PDT 24 134459531 ps
T879 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1465694918 Jul 28 05:11:45 PM PDT 24 Jul 28 05:11:46 PM PDT 24 53579170 ps
T880 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2543022398 Jul 28 05:11:49 PM PDT 24 Jul 28 05:11:50 PM PDT 24 280759211 ps
T881 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.4243858889 Jul 28 05:11:48 PM PDT 24 Jul 28 05:11:49 PM PDT 24 689344345 ps
T882 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3913080365 Jul 28 05:11:51 PM PDT 24 Jul 28 05:11:52 PM PDT 24 34263339 ps
T883 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3805831501 Jul 28 05:11:42 PM PDT 24 Jul 28 05:11:43 PM PDT 24 38620742 ps
T884 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2045995528 Jul 28 05:11:53 PM PDT 24 Jul 28 05:11:54 PM PDT 24 141332422 ps
T885 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3651744798 Jul 28 05:11:36 PM PDT 24 Jul 28 05:11:37 PM PDT 24 66826792 ps
T886 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2479282519 Jul 28 05:11:59 PM PDT 24 Jul 28 05:12:00 PM PDT 24 276888011 ps
T887 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.99263320 Jul 28 05:12:02 PM PDT 24 Jul 28 05:12:03 PM PDT 24 93285227 ps
T888 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.208095892 Jul 28 05:11:44 PM PDT 24 Jul 28 05:11:45 PM PDT 24 38538314 ps
T889 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1902932770 Jul 28 05:11:26 PM PDT 24 Jul 28 05:11:28 PM PDT 24 70225229 ps
T890 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2073613569 Jul 28 05:11:48 PM PDT 24 Jul 28 05:11:49 PM PDT 24 39566159 ps
T891 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.698690433 Jul 28 05:12:02 PM PDT 24 Jul 28 05:12:03 PM PDT 24 29451752 ps
T892 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.331938369 Jul 28 05:12:04 PM PDT 24 Jul 28 05:12:05 PM PDT 24 185139259 ps
T893 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1223734567 Jul 28 05:12:09 PM PDT 24 Jul 28 05:12:10 PM PDT 24 34788185 ps
T894 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3198064760 Jul 28 05:11:43 PM PDT 24 Jul 28 05:11:44 PM PDT 24 273357424 ps
T895 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2306122121 Jul 28 05:11:50 PM PDT 24 Jul 28 05:11:51 PM PDT 24 45408145 ps
T896 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3442300716 Jul 28 05:11:40 PM PDT 24 Jul 28 05:11:41 PM PDT 24 19698350 ps
T897 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1007352384 Jul 28 05:11:49 PM PDT 24 Jul 28 05:11:50 PM PDT 24 122321115 ps
T898 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1595365365 Jul 28 05:11:55 PM PDT 24 Jul 28 05:11:56 PM PDT 24 80356710 ps
T899 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.744251208 Jul 28 05:11:54 PM PDT 24 Jul 28 05:11:55 PM PDT 24 48011986 ps
T900 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2877525590 Jul 28 05:11:54 PM PDT 24 Jul 28 05:11:55 PM PDT 24 134123129 ps
T901 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1026158207 Jul 28 05:12:09 PM PDT 24 Jul 28 05:12:10 PM PDT 24 284240257 ps
T902 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.48787665 Jul 28 05:11:55 PM PDT 24 Jul 28 05:11:56 PM PDT 24 53231332 ps
T903 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2539858354 Jul 28 05:11:53 PM PDT 24 Jul 28 05:11:54 PM PDT 24 69621719 ps
T904 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3864944355 Jul 28 05:11:52 PM PDT 24 Jul 28 05:11:54 PM PDT 24 337498216 ps
T905 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2539117705 Jul 28 05:11:51 PM PDT 24 Jul 28 05:11:53 PM PDT 24 47666519 ps
T906 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1799286620 Jul 28 05:11:57 PM PDT 24 Jul 28 05:11:58 PM PDT 24 252317135 ps
T907 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.4111036769 Jul 28 05:12:12 PM PDT 24 Jul 28 05:12:13 PM PDT 24 112489565 ps
T908 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2256399691 Jul 28 05:11:33 PM PDT 24 Jul 28 05:11:34 PM PDT 24 141022934 ps
T909 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2247499964 Jul 28 05:11:48 PM PDT 24 Jul 28 05:11:49 PM PDT 24 159095908 ps
T910 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.295617205 Jul 28 05:11:42 PM PDT 24 Jul 28 05:11:43 PM PDT 24 93841067 ps
T911 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1766200545 Jul 28 05:11:38 PM PDT 24 Jul 28 05:11:39 PM PDT 24 74963142 ps
T912 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1768851494 Jul 28 05:11:43 PM PDT 24 Jul 28 05:11:44 PM PDT 24 48857482 ps
T913 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1928169277 Jul 28 05:11:38 PM PDT 24 Jul 28 05:11:39 PM PDT 24 156568011 ps
T914 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1313698707 Jul 28 05:12:06 PM PDT 24 Jul 28 05:12:07 PM PDT 24 48038910 ps
T915 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3685336497 Jul 28 05:11:48 PM PDT 24 Jul 28 05:11:49 PM PDT 24 101397270 ps
T916 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1236948285 Jul 28 05:12:08 PM PDT 24 Jul 28 05:12:09 PM PDT 24 24211681 ps
T917 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1644312885 Jul 28 05:11:49 PM PDT 24 Jul 28 05:11:50 PM PDT 24 127514330 ps
T918 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3367936101 Jul 28 05:11:35 PM PDT 24 Jul 28 05:11:36 PM PDT 24 25529884 ps
T919 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3787453007 Jul 28 05:12:00 PM PDT 24 Jul 28 05:12:01 PM PDT 24 149229525 ps
T920 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1168277311 Jul 28 05:11:42 PM PDT 24 Jul 28 05:11:43 PM PDT 24 86715437 ps
T921 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2490971327 Jul 28 05:11:51 PM PDT 24 Jul 28 05:11:53 PM PDT 24 139112392 ps
T922 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3338078332 Jul 28 05:11:39 PM PDT 24 Jul 28 05:11:40 PM PDT 24 51122833 ps
T923 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1024741992 Jul 28 05:11:55 PM PDT 24 Jul 28 05:11:57 PM PDT 24 445701072 ps
T924 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.105314531 Jul 28 05:11:46 PM PDT 24 Jul 28 05:11:47 PM PDT 24 464668523 ps
T925 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.442445393 Jul 28 05:11:59 PM PDT 24 Jul 28 05:12:01 PM PDT 24 316587349 ps
T926 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1709133757 Jul 28 05:11:48 PM PDT 24 Jul 28 05:11:49 PM PDT 24 60638272 ps
T927 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3215953904 Jul 28 05:11:55 PM PDT 24 Jul 28 05:11:56 PM PDT 24 42753410 ps
T928 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2717153484 Jul 28 05:11:40 PM PDT 24 Jul 28 05:11:42 PM PDT 24 480557495 ps
T929 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1050178363 Jul 28 05:11:50 PM PDT 24 Jul 28 05:11:51 PM PDT 24 71692151 ps
T930 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1314596591 Jul 28 05:11:39 PM PDT 24 Jul 28 05:11:40 PM PDT 24 71452572 ps
T931 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.780436126 Jul 28 05:11:45 PM PDT 24 Jul 28 05:11:47 PM PDT 24 57934885 ps
T932 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1001328683 Jul 28 05:11:55 PM PDT 24 Jul 28 05:11:56 PM PDT 24 17277125 ps
T933 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.93637157 Jul 28 05:12:06 PM PDT 24 Jul 28 05:12:07 PM PDT 24 687250782 ps
T934 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3057403711 Jul 28 05:12:04 PM PDT 24 Jul 28 05:12:06 PM PDT 24 74062846 ps
T935 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1630126218 Jul 28 05:11:40 PM PDT 24 Jul 28 05:11:41 PM PDT 24 143600168 ps
T936 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.974119289 Jul 28 05:11:31 PM PDT 24 Jul 28 05:11:33 PM PDT 24 440876502 ps
T937 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.694527423 Jul 28 05:11:49 PM PDT 24 Jul 28 05:11:50 PM PDT 24 35751156 ps
T938 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1151743900 Jul 28 05:11:44 PM PDT 24 Jul 28 05:11:45 PM PDT 24 68002128 ps
T939 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1247657391 Jul 28 05:11:39 PM PDT 24 Jul 28 05:11:40 PM PDT 24 115753797 ps
T940 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.87826689 Jul 28 05:11:52 PM PDT 24 Jul 28 05:11:53 PM PDT 24 147441076 ps
T941 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.237521866 Jul 28 05:11:42 PM PDT 24 Jul 28 05:11:44 PM PDT 24 46095401 ps
T942 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2179803461 Jul 28 05:11:48 PM PDT 24 Jul 28 05:11:49 PM PDT 24 59054553 ps
T943 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3438122519 Jul 28 05:11:52 PM PDT 24 Jul 28 05:11:53 PM PDT 24 37526002 ps

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.2148389677
Short name T13
Test name
Test status
Simulation time 138319842056 ps
CPU time 887.91 seconds
Started Jul 28 05:14:33 PM PDT 24
Finished Jul 28 05:29:21 PM PDT 24
Peak memory 198616 kb
Host smart-2b35e6e3-780d-43db-a0f5-060eea009f2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2148389677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.2148389677
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2429933418
Short name T28
Test name
Test status
Simulation time 267812033 ps
CPU time 2.78 seconds
Started Jul 28 05:13:30 PM PDT 24
Finished Jul 28 05:13:33 PM PDT 24
Peak memory 198580 kb
Host smart-ee867a0d-c956-4753-8ca4-e21c9b2a0044
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429933418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2429933418
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.4212170131
Short name T25
Test name
Test status
Simulation time 316966116 ps
CPU time 0.89 seconds
Started Jul 28 05:13:33 PM PDT 24
Finished Jul 28 05:13:34 PM PDT 24
Peak memory 214480 kb
Host smart-e1d26fdb-153f-4e5e-be0c-fc035a21d6d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212170131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.4212170131
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/35.gpio_stress_all.4076737511
Short name T1
Test name
Test status
Simulation time 1600492118 ps
CPU time 17.31 seconds
Started Jul 28 05:14:44 PM PDT 24
Finished Jul 28 05:15:01 PM PDT 24
Peak memory 198608 kb
Host smart-bc315bcf-c2f7-42e6-9bb1-53035cb6c366
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076737511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.4076737511
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1926145592
Short name T64
Test name
Test status
Simulation time 14014769 ps
CPU time 0.64 seconds
Started Jul 28 05:11:26 PM PDT 24
Finished Jul 28 05:11:26 PM PDT 24
Peak memory 195656 kb
Host smart-d30678e9-3057-4f4f-96d5-9b9af0505d46
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926145592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1926145592
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.4216256916
Short name T40
Test name
Test status
Simulation time 164617679 ps
CPU time 1.44 seconds
Started Jul 28 05:11:34 PM PDT 24
Finished Jul 28 05:11:36 PM PDT 24
Peak memory 198368 kb
Host smart-bf2917cc-ee46-4358-bb04-274bd1f9a38e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216256916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.4216256916
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1133958721
Short name T15
Test name
Test status
Simulation time 31278401 ps
CPU time 0.58 seconds
Started Jul 28 05:14:48 PM PDT 24
Finished Jul 28 05:14:49 PM PDT 24
Peak memory 194556 kb
Host smart-d5768ee5-273c-40a6-80b2-8ba6bccea251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133958721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1133958721
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3496964818
Short name T80
Test name
Test status
Simulation time 27110306 ps
CPU time 0.77 seconds
Started Jul 28 05:11:23 PM PDT 24
Finished Jul 28 05:11:24 PM PDT 24
Peak memory 195972 kb
Host smart-5e2661c2-cca5-45fa-be83-f532e25ec6f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496964818 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3496964818
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3939720982
Short name T77
Test name
Test status
Simulation time 11046003 ps
CPU time 0.57 seconds
Started Jul 28 05:11:23 PM PDT 24
Finished Jul 28 05:11:24 PM PDT 24
Peak memory 193644 kb
Host smart-0e84a38c-883a-4def-b10a-43857a946e15
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939720982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.3939720982
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2374810233
Short name T808
Test name
Test status
Simulation time 446934812 ps
CPU time 1.15 seconds
Started Jul 28 05:11:26 PM PDT 24
Finished Jul 28 05:11:27 PM PDT 24
Peak memory 198376 kb
Host smart-15bcbdcd-c519-48fd-8939-53fed3fc8271
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374810233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2374810233
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1684024433
Short name T37
Test name
Test status
Simulation time 228161881 ps
CPU time 1.47 seconds
Started Jul 28 05:11:28 PM PDT 24
Finished Jul 28 05:11:30 PM PDT 24
Peak memory 198384 kb
Host smart-fb3e4479-d62c-42d8-984c-2995aac09c83
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684024433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1684024433
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.796896298
Short name T61
Test name
Test status
Simulation time 16354404 ps
CPU time 0.67 seconds
Started Jul 28 05:11:33 PM PDT 24
Finished Jul 28 05:11:34 PM PDT 24
Peak memory 195104 kb
Host smart-d7884a7d-26fd-4947-a035-932643cadef7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796896298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.796896298
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.4098503946
Short name T763
Test name
Test status
Simulation time 193047560 ps
CPU time 1.4 seconds
Started Jul 28 05:11:24 PM PDT 24
Finished Jul 28 05:11:25 PM PDT 24
Peak memory 197200 kb
Host smart-cf5f466c-f3ca-4ddd-a634-452808406346
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098503946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.4098503946
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3895560965
Short name T759
Test name
Test status
Simulation time 15890991 ps
CPU time 0.63 seconds
Started Jul 28 05:11:26 PM PDT 24
Finished Jul 28 05:11:27 PM PDT 24
Peak memory 195320 kb
Host smart-b4e51d4d-fb00-4e4b-88d7-c203af5b3fab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895560965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3895560965
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.396441062
Short name T803
Test name
Test status
Simulation time 33589594 ps
CPU time 1.64 seconds
Started Jul 28 05:11:27 PM PDT 24
Finished Jul 28 05:11:28 PM PDT 24
Peak memory 198400 kb
Host smart-6a2cb3ad-07d7-4b9c-91ff-423139df0697
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396441062 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.396441062
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2843679552
Short name T722
Test name
Test status
Simulation time 16390531 ps
CPU time 0.59 seconds
Started Jul 28 05:11:20 PM PDT 24
Finished Jul 28 05:11:21 PM PDT 24
Peak memory 194112 kb
Host smart-f2664b52-cf7c-41dc-a15c-3d4ddd88a8a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843679552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2843679552
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.887788014
Short name T774
Test name
Test status
Simulation time 44217607 ps
CPU time 0.95 seconds
Started Jul 28 05:11:13 PM PDT 24
Finished Jul 28 05:11:15 PM PDT 24
Peak memory 198352 kb
Host smart-1553299e-3ec9-437e-90da-db409189c415
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887788014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.887788014
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1049006875
Short name T30
Test name
Test status
Simulation time 150934731 ps
CPU time 1.09 seconds
Started Jul 28 05:11:21 PM PDT 24
Finished Jul 28 05:11:22 PM PDT 24
Peak memory 198344 kb
Host smart-90a3c446-ddf0-40fc-bf9e-6a36680c5768
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049006875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1049006875
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2318981458
Short name T843
Test name
Test status
Simulation time 47843734 ps
CPU time 0.73 seconds
Started Jul 28 05:11:26 PM PDT 24
Finished Jul 28 05:11:27 PM PDT 24
Peak memory 195952 kb
Host smart-61ccc3b2-b30c-415e-8805-5d98fba17fe4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318981458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2318981458
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.635149470
Short name T75
Test name
Test status
Simulation time 79256070 ps
CPU time 2.85 seconds
Started Jul 28 05:11:24 PM PDT 24
Finished Jul 28 05:11:27 PM PDT 24
Peak memory 197320 kb
Host smart-a550d1a0-6763-4685-a377-4284a1d0f7c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635149470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.635149470
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.911621880
Short name T72
Test name
Test status
Simulation time 14268618 ps
CPU time 0.63 seconds
Started Jul 28 05:11:15 PM PDT 24
Finished Jul 28 05:11:16 PM PDT 24
Peak memory 194928 kb
Host smart-c294c6b8-9fd4-4cc1-a456-86aa821031ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911621880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.911621880
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1624395930
Short name T723
Test name
Test status
Simulation time 25733383 ps
CPU time 1.13 seconds
Started Jul 28 05:11:27 PM PDT 24
Finished Jul 28 05:11:28 PM PDT 24
Peak memory 198368 kb
Host smart-27757cf7-a8ed-41c5-a184-026544da31bc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624395930 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1624395930
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2221315280
Short name T60
Test name
Test status
Simulation time 44450885 ps
CPU time 0.63 seconds
Started Jul 28 05:11:21 PM PDT 24
Finished Jul 28 05:11:22 PM PDT 24
Peak memory 195240 kb
Host smart-9f0dfe95-eafc-42ab-8a07-70e495a9f381
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221315280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2221315280
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1916990270
Short name T741
Test name
Test status
Simulation time 28707754 ps
CPU time 0.57 seconds
Started Jul 28 05:11:34 PM PDT 24
Finished Jul 28 05:11:35 PM PDT 24
Peak memory 194024 kb
Host smart-3f6f7bf9-b5ca-4d9e-81f4-ef74fcc86175
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916990270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1916990270
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2414428093
Short name T63
Test name
Test status
Simulation time 68196646 ps
CPU time 0.86 seconds
Started Jul 28 05:11:25 PM PDT 24
Finished Jul 28 05:11:26 PM PDT 24
Peak memory 196524 kb
Host smart-f92a99d9-02ae-4ff9-824a-10fed08db128
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414428093 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.2414428093
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2363833606
Short name T837
Test name
Test status
Simulation time 63736452 ps
CPU time 1.31 seconds
Started Jul 28 05:11:28 PM PDT 24
Finished Jul 28 05:11:29 PM PDT 24
Peak memory 198392 kb
Host smart-6d45b975-3ecc-4ba6-bd53-c66bd3625d3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363833606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2363833606
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1508603538
Short name T41
Test name
Test status
Simulation time 149595651 ps
CPU time 1.07 seconds
Started Jul 28 05:11:25 PM PDT 24
Finished Jul 28 05:11:26 PM PDT 24
Peak memory 198316 kb
Host smart-bcb99427-cb44-464c-a1b1-1550316e6c96
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508603538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1508603538
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3507673838
Short name T794
Test name
Test status
Simulation time 52581697 ps
CPU time 0.81 seconds
Started Jul 28 05:11:18 PM PDT 24
Finished Jul 28 05:11:19 PM PDT 24
Peak memory 198180 kb
Host smart-b515ac23-70fc-4178-bddd-63d461bb69de
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507673838 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3507673838
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3420074616
Short name T791
Test name
Test status
Simulation time 22749781 ps
CPU time 0.57 seconds
Started Jul 28 05:11:31 PM PDT 24
Finished Jul 28 05:11:31 PM PDT 24
Peak memory 194152 kb
Host smart-33074ec4-f04f-4d05-b596-9136a397a835
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420074616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3420074616
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.652571876
Short name T730
Test name
Test status
Simulation time 31300892 ps
CPU time 0.55 seconds
Started Jul 28 05:11:30 PM PDT 24
Finished Jul 28 05:11:31 PM PDT 24
Peak memory 194640 kb
Host smart-67a95810-4211-4a11-80b4-25c201c8333c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652571876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.652571876
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3014590182
Short name T81
Test name
Test status
Simulation time 35115451 ps
CPU time 0.84 seconds
Started Jul 28 05:11:23 PM PDT 24
Finished Jul 28 05:11:24 PM PDT 24
Peak memory 196452 kb
Host smart-0161c301-4254-4f7c-b500-86fdf6260812
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014590182 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3014590182
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3077019799
Short name T751
Test name
Test status
Simulation time 71686695 ps
CPU time 1.65 seconds
Started Jul 28 05:11:23 PM PDT 24
Finished Jul 28 05:11:25 PM PDT 24
Peak memory 198356 kb
Host smart-22e75a27-f13a-4ed7-b61c-5c914ea8fae6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077019799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3077019799
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1831781600
Short name T819
Test name
Test status
Simulation time 132458435 ps
CPU time 0.84 seconds
Started Jul 28 05:11:36 PM PDT 24
Finished Jul 28 05:11:42 PM PDT 24
Peak memory 198096 kb
Host smart-a2ef7c06-043b-49f0-b683-0058d53ea519
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831781600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1831781600
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1641284469
Short name T820
Test name
Test status
Simulation time 23912844 ps
CPU time 0.98 seconds
Started Jul 28 05:11:22 PM PDT 24
Finished Jul 28 05:11:23 PM PDT 24
Peak memory 198144 kb
Host smart-0aa4093e-e09e-42b0-a0cc-b18ea1840088
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641284469 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.1641284469
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.167016733
Short name T833
Test name
Test status
Simulation time 32134434 ps
CPU time 0.56 seconds
Started Jul 28 05:11:19 PM PDT 24
Finished Jul 28 05:11:19 PM PDT 24
Peak memory 194964 kb
Host smart-a05de573-4dc8-46d8-ad64-c82ba2a89529
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167016733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.167016733
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.559947568
Short name T778
Test name
Test status
Simulation time 75182720 ps
CPU time 0.63 seconds
Started Jul 28 05:11:23 PM PDT 24
Finished Jul 28 05:11:24 PM PDT 24
Peak memory 194028 kb
Host smart-536f98e8-2186-4ffc-8012-7fb1617e38b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559947568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.559947568
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.90190039
Short name T756
Test name
Test status
Simulation time 18837572 ps
CPU time 0.72 seconds
Started Jul 28 05:11:32 PM PDT 24
Finished Jul 28 05:11:33 PM PDT 24
Peak memory 196284 kb
Host smart-994e0fa1-7ca9-48c1-a613-d315e8cf3364
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90190039 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.gpio_same_csr_outstanding.90190039
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.269750603
Short name T765
Test name
Test status
Simulation time 222297291 ps
CPU time 1.28 seconds
Started Jul 28 05:11:23 PM PDT 24
Finished Jul 28 05:11:24 PM PDT 24
Peak memory 198316 kb
Host smart-1fd6517c-5d18-4d16-84be-0aecc177b0d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269750603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.269750603
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3267528662
Short name T44
Test name
Test status
Simulation time 152475606 ps
CPU time 1.06 seconds
Started Jul 28 05:11:24 PM PDT 24
Finished Jul 28 05:11:26 PM PDT 24
Peak memory 198352 kb
Host smart-a6dbc15c-e5bf-42db-b53c-75ccc5e196e7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267528662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3267528662
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2889151195
Short name T798
Test name
Test status
Simulation time 172145424 ps
CPU time 1.16 seconds
Started Jul 28 05:11:42 PM PDT 24
Finished Jul 28 05:11:43 PM PDT 24
Peak memory 198432 kb
Host smart-782cee2d-d27a-4ea0-a8be-2efc8083629f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889151195 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2889151195
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.376534070
Short name T71
Test name
Test status
Simulation time 56299195 ps
CPU time 0.6 seconds
Started Jul 28 05:11:34 PM PDT 24
Finished Jul 28 05:11:35 PM PDT 24
Peak memory 195036 kb
Host smart-417da2c5-9817-44b6-bab8-01f8ad0d3af4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376534070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.376534070
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.745202194
Short name T725
Test name
Test status
Simulation time 14632576 ps
CPU time 0.62 seconds
Started Jul 28 05:11:24 PM PDT 24
Finished Jul 28 05:11:25 PM PDT 24
Peak memory 194052 kb
Host smart-e1070bfe-1a46-49ef-9c89-2de1d95cad06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745202194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.745202194
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.4047536090
Short name T828
Test name
Test status
Simulation time 225880669 ps
CPU time 0.79 seconds
Started Jul 28 05:11:28 PM PDT 24
Finished Jul 28 05:11:29 PM PDT 24
Peak memory 196624 kb
Host smart-492cae02-b5fe-4a11-83d1-da119c4c1e77
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047536090 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.4047536090
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2881465496
Short name T737
Test name
Test status
Simulation time 304315679 ps
CPU time 2.79 seconds
Started Jul 28 05:11:27 PM PDT 24
Finished Jul 28 05:11:35 PM PDT 24
Peak memory 198364 kb
Host smart-dc75038a-2cb2-4d91-8ac9-1cecaca66d56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881465496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2881465496
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.380479170
Short name T32
Test name
Test status
Simulation time 45256718 ps
CPU time 0.83 seconds
Started Jul 28 05:11:36 PM PDT 24
Finished Jul 28 05:11:37 PM PDT 24
Peak memory 197516 kb
Host smart-a733aada-da50-443f-8615-75d72b8c9bb8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380479170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.380479170
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1942601404
Short name T800
Test name
Test status
Simulation time 35324285 ps
CPU time 0.85 seconds
Started Jul 28 05:11:29 PM PDT 24
Finished Jul 28 05:11:30 PM PDT 24
Peak memory 198136 kb
Host smart-941d2374-7804-4a60-ae68-683486a97c2b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942601404 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1942601404
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3506162431
Short name T73
Test name
Test status
Simulation time 15093773 ps
CPU time 0.61 seconds
Started Jul 28 05:11:31 PM PDT 24
Finished Jul 28 05:11:32 PM PDT 24
Peak memory 194992 kb
Host smart-a9886187-f288-498e-90db-ce21bcefaab5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506162431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3506162431
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.3149296049
Short name T769
Test name
Test status
Simulation time 14862983 ps
CPU time 0.6 seconds
Started Jul 28 05:11:57 PM PDT 24
Finished Jul 28 05:11:58 PM PDT 24
Peak memory 194300 kb
Host smart-5825cd72-5df2-4ff6-a5a7-d26c37dcdec3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149296049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.3149296049
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1391816994
Short name T55
Test name
Test status
Simulation time 122125707 ps
CPU time 0.67 seconds
Started Jul 28 05:11:39 PM PDT 24
Finished Jul 28 05:11:39 PM PDT 24
Peak memory 195332 kb
Host smart-15a4813f-4fb9-4bb0-b6be-4c9b2a7e182d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391816994 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1391816994
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3377082714
Short name T838
Test name
Test status
Simulation time 166780886 ps
CPU time 2.74 seconds
Started Jul 28 05:11:41 PM PDT 24
Finished Jul 28 05:11:44 PM PDT 24
Peak memory 198320 kb
Host smart-cbe58ee8-bc15-460c-a0d2-8f20827fe702
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377082714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.3377082714
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2170550813
Short name T42
Test name
Test status
Simulation time 68447043 ps
CPU time 1.09 seconds
Started Jul 28 05:11:26 PM PDT 24
Finished Jul 28 05:11:27 PM PDT 24
Peak memory 198372 kb
Host smart-1f615bcc-7142-4963-8590-e20d0248fe1d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170550813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2170550813
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3505683330
Short name T729
Test name
Test status
Simulation time 155073845 ps
CPU time 0.67 seconds
Started Jul 28 05:11:19 PM PDT 24
Finished Jul 28 05:11:20 PM PDT 24
Peak memory 196960 kb
Host smart-512d3224-ecb1-4b90-9b7d-ee3070abc419
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505683330 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3505683330
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3519839885
Short name T67
Test name
Test status
Simulation time 14195874 ps
CPU time 0.58 seconds
Started Jul 28 05:11:27 PM PDT 24
Finished Jul 28 05:11:28 PM PDT 24
Peak memory 193616 kb
Host smart-a8d1f216-29b3-442f-9b8b-a164749691f9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519839885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.3519839885
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.3097793899
Short name T821
Test name
Test status
Simulation time 76387319 ps
CPU time 0.58 seconds
Started Jul 28 05:11:26 PM PDT 24
Finished Jul 28 05:11:26 PM PDT 24
Peak memory 194720 kb
Host smart-9e0770bc-c44b-452e-9e26-e7ea62c4718a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097793899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.3097793899
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3004644607
Short name T801
Test name
Test status
Simulation time 21345118 ps
CPU time 0.64 seconds
Started Jul 28 05:11:44 PM PDT 24
Finished Jul 28 05:11:45 PM PDT 24
Peak memory 194884 kb
Host smart-763458a5-bff3-4a3b-aba8-a12d06d29f54
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004644607 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3004644607
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2865919858
Short name T817
Test name
Test status
Simulation time 156471905 ps
CPU time 3.04 seconds
Started Jul 28 05:11:20 PM PDT 24
Finished Jul 28 05:11:24 PM PDT 24
Peak memory 198388 kb
Host smart-3cc24267-87f3-4151-8be4-33d751cf2d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865919858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2865919858
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.4084121278
Short name T831
Test name
Test status
Simulation time 360744692 ps
CPU time 1.42 seconds
Started Jul 28 05:11:28 PM PDT 24
Finished Jul 28 05:11:29 PM PDT 24
Peak memory 198244 kb
Host smart-21888baa-5d27-4ccb-bc4e-1a37d79f7a7d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084121278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.4084121278
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3982757613
Short name T785
Test name
Test status
Simulation time 77158020 ps
CPU time 0.96 seconds
Started Jul 28 05:11:29 PM PDT 24
Finished Jul 28 05:11:30 PM PDT 24
Peak memory 198160 kb
Host smart-eff29339-5c2c-476f-a923-e3953ace68c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982757613 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3982757613
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.803026136
Short name T762
Test name
Test status
Simulation time 46052172 ps
CPU time 0.62 seconds
Started Jul 28 05:11:29 PM PDT 24
Finished Jul 28 05:11:29 PM PDT 24
Peak memory 195776 kb
Host smart-aed3700e-a35e-4a80-b6e8-01a4081fc524
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803026136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio
_csr_rw.803026136
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.4294882388
Short name T753
Test name
Test status
Simulation time 23069889 ps
CPU time 0.61 seconds
Started Jul 28 05:11:40 PM PDT 24
Finished Jul 28 05:11:41 PM PDT 24
Peak memory 194084 kb
Host smart-507cd150-bfa4-4749-a6f1-13104297af25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294882388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.4294882388
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1793315175
Short name T82
Test name
Test status
Simulation time 37340330 ps
CPU time 0.63 seconds
Started Jul 28 05:11:38 PM PDT 24
Finished Jul 28 05:11:38 PM PDT 24
Peak memory 195072 kb
Host smart-6c762c48-9653-49bb-9558-d6e136c3fa9a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793315175 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1793315175
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.381226613
Short name T740
Test name
Test status
Simulation time 62454802 ps
CPU time 1.41 seconds
Started Jul 28 05:11:46 PM PDT 24
Finished Jul 28 05:11:47 PM PDT 24
Peak memory 198320 kb
Host smart-92ef0bf0-b2e9-4fc7-9c55-a245d7665dbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381226613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.381226613
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.124859385
Short name T825
Test name
Test status
Simulation time 96719983 ps
CPU time 1.34 seconds
Started Jul 28 05:11:40 PM PDT 24
Finished Jul 28 05:11:46 PM PDT 24
Peak memory 198416 kb
Host smart-33014a59-f8dd-47ff-ad91-4bf1ace1e318
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124859385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.124859385
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.39015217
Short name T734
Test name
Test status
Simulation time 30945119 ps
CPU time 1.36 seconds
Started Jul 28 05:11:31 PM PDT 24
Finished Jul 28 05:11:32 PM PDT 24
Peak memory 198404 kb
Host smart-8a725901-1150-4ea6-8910-3afc1e243f84
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39015217 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.39015217
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.868295469
Short name T840
Test name
Test status
Simulation time 74609259 ps
CPU time 0.58 seconds
Started Jul 28 05:11:32 PM PDT 24
Finished Jul 28 05:11:32 PM PDT 24
Peak memory 194280 kb
Host smart-46465d6c-0e59-4508-9ff4-93c20d2cdb56
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868295469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.868295469
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.39068598
Short name T764
Test name
Test status
Simulation time 13475950 ps
CPU time 0.63 seconds
Started Jul 28 05:11:33 PM PDT 24
Finished Jul 28 05:11:34 PM PDT 24
Peak memory 194048 kb
Host smart-40c96116-c773-48ea-a1aa-9059fe7c4672
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39068598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.39068598
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2482756815
Short name T62
Test name
Test status
Simulation time 24004323 ps
CPU time 0.66 seconds
Started Jul 28 05:11:30 PM PDT 24
Finished Jul 28 05:11:31 PM PDT 24
Peak memory 196056 kb
Host smart-51a728ad-4d58-428e-b28b-7536bb7be521
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482756815 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2482756815
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1754046131
Short name T815
Test name
Test status
Simulation time 35956997 ps
CPU time 1.72 seconds
Started Jul 28 05:11:45 PM PDT 24
Finished Jul 28 05:11:46 PM PDT 24
Peak memory 198360 kb
Host smart-3d0c752c-6f21-4633-9c63-0000a67dc16a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754046131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1754046131
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3684995244
Short name T776
Test name
Test status
Simulation time 25348988 ps
CPU time 0.77 seconds
Started Jul 28 05:11:37 PM PDT 24
Finished Jul 28 05:11:38 PM PDT 24
Peak memory 198256 kb
Host smart-abca33fe-9e52-4ee7-b1a0-4cc062260f96
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684995244 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3684995244
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2127397431
Short name T768
Test name
Test status
Simulation time 24304828 ps
CPU time 0.57 seconds
Started Jul 28 05:11:26 PM PDT 24
Finished Jul 28 05:11:27 PM PDT 24
Peak memory 195396 kb
Host smart-6a894dde-eaf4-432b-b126-fbc8508ebd8f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127397431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2127397431
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3676446300
Short name T788
Test name
Test status
Simulation time 14962119 ps
CPU time 0.6 seconds
Started Jul 28 05:11:41 PM PDT 24
Finished Jul 28 05:11:41 PM PDT 24
Peak memory 194128 kb
Host smart-7b1c72b0-9c1c-4617-b7bc-084a0cc41953
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676446300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3676446300
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1674219096
Short name T777
Test name
Test status
Simulation time 117792812 ps
CPU time 0.77 seconds
Started Jul 28 05:11:24 PM PDT 24
Finished Jul 28 05:11:25 PM PDT 24
Peak memory 197116 kb
Host smart-094e225a-de37-472f-9403-bd15599d7a2a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674219096 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.1674219096
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2425409195
Short name T732
Test name
Test status
Simulation time 237622537 ps
CPU time 1.36 seconds
Started Jul 28 05:11:31 PM PDT 24
Finished Jul 28 05:11:33 PM PDT 24
Peak memory 198368 kb
Host smart-12817968-0073-47df-9eca-b2cb15cea949
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425409195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2425409195
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.516320059
Short name T809
Test name
Test status
Simulation time 152405440 ps
CPU time 0.84 seconds
Started Jul 28 05:11:43 PM PDT 24
Finished Jul 28 05:11:44 PM PDT 24
Peak memory 197584 kb
Host smart-1bddb500-031f-4ebc-877d-72e49ad429fe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516320059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.gpio_tl_intg_err.516320059
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.378301968
Short name T802
Test name
Test status
Simulation time 30588777 ps
CPU time 0.82 seconds
Started Jul 28 05:11:31 PM PDT 24
Finished Jul 28 05:11:32 PM PDT 24
Peak memory 198240 kb
Host smart-7cfb1279-0df3-4ac8-a639-23cf5439a3a0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378301968 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.378301968
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3395337674
Short name T760
Test name
Test status
Simulation time 15414618 ps
CPU time 0.6 seconds
Started Jul 28 05:11:29 PM PDT 24
Finished Jul 28 05:11:30 PM PDT 24
Peak memory 194832 kb
Host smart-6b7efe7f-9c80-4994-8a50-406380290dce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395337674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3395337674
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.129047906
Short name T738
Test name
Test status
Simulation time 41712674 ps
CPU time 0.6 seconds
Started Jul 28 05:11:38 PM PDT 24
Finished Jul 28 05:11:39 PM PDT 24
Peak memory 193980 kb
Host smart-65787fca-af60-48e7-a244-25947184ea02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129047906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.129047906
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2011101635
Short name T57
Test name
Test status
Simulation time 16757460 ps
CPU time 0.76 seconds
Started Jul 28 05:11:48 PM PDT 24
Finished Jul 28 05:11:48 PM PDT 24
Peak memory 196564 kb
Host smart-be310297-7542-4c96-9d29-649c376cb4c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011101635 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2011101635
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2015665
Short name T766
Test name
Test status
Simulation time 325277463 ps
CPU time 2.96 seconds
Started Jul 28 05:11:37 PM PDT 24
Finished Jul 28 05:11:40 PM PDT 24
Peak memory 198304 kb
Host smart-de9c30dd-3185-45e3-b36d-23de05220bd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.2015665
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.4215360632
Short name T43
Test name
Test status
Simulation time 78381969 ps
CPU time 1.16 seconds
Started Jul 28 05:11:37 PM PDT 24
Finished Jul 28 05:11:39 PM PDT 24
Peak memory 198552 kb
Host smart-e2808a3d-3fd3-4adb-985b-5ba604338488
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215360632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.4215360632
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3610796468
Short name T793
Test name
Test status
Simulation time 26272140 ps
CPU time 0.97 seconds
Started Jul 28 05:11:37 PM PDT 24
Finished Jul 28 05:11:38 PM PDT 24
Peak memory 193348 kb
Host smart-63bef594-6dc3-42c6-a99a-3e94002183d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610796468 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3610796468
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4148360260
Short name T76
Test name
Test status
Simulation time 17031082 ps
CPU time 0.68 seconds
Started Jul 28 05:11:28 PM PDT 24
Finished Jul 28 05:11:29 PM PDT 24
Peak memory 195060 kb
Host smart-09506278-f415-4f09-9555-c114821135e7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148360260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.4148360260
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.2397373822
Short name T731
Test name
Test status
Simulation time 17398703 ps
CPU time 0.6 seconds
Started Jul 28 05:11:36 PM PDT 24
Finished Jul 28 05:11:37 PM PDT 24
Peak memory 194696 kb
Host smart-0275be9d-dd93-4658-8a68-39e813cb27db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397373822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.2397373822
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3650737339
Short name T807
Test name
Test status
Simulation time 42036016 ps
CPU time 0.84 seconds
Started Jul 28 05:11:48 PM PDT 24
Finished Jul 28 05:11:49 PM PDT 24
Peak memory 197496 kb
Host smart-c9caf8e7-e830-4363-8944-45f8c036ffb3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650737339 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3650737339
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.228539040
Short name T787
Test name
Test status
Simulation time 69222807 ps
CPU time 1.67 seconds
Started Jul 28 05:11:29 PM PDT 24
Finished Jul 28 05:11:31 PM PDT 24
Peak memory 198284 kb
Host smart-2ffbab96-27a7-4dc6-8e0c-636c44851cbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228539040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.228539040
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3371935169
Short name T39
Test name
Test status
Simulation time 214806514 ps
CPU time 1.4 seconds
Started Jul 28 05:11:41 PM PDT 24
Finished Jul 28 05:11:43 PM PDT 24
Peak memory 198420 kb
Host smart-2ac0e5bf-79d6-421f-a2a3-b1228e78830d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371935169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3371935169
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3114671828
Short name T69
Test name
Test status
Simulation time 24170534 ps
CPU time 0.73 seconds
Started Jul 28 05:11:20 PM PDT 24
Finished Jul 28 05:11:21 PM PDT 24
Peak memory 196284 kb
Host smart-509a1da6-550e-4de2-af70-e3aae4edd05a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114671828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.3114671828
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2008853029
Short name T74
Test name
Test status
Simulation time 458776117 ps
CPU time 2.89 seconds
Started Jul 28 05:11:32 PM PDT 24
Finished Jul 28 05:11:35 PM PDT 24
Peak memory 197288 kb
Host smart-8bbc0255-f46c-4cda-a4ae-c19930ed57f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008853029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2008853029
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.251458389
Short name T750
Test name
Test status
Simulation time 32134410 ps
CPU time 0.67 seconds
Started Jul 28 05:11:31 PM PDT 24
Finished Jul 28 05:11:32 PM PDT 24
Peak memory 195816 kb
Host smart-715364c9-e036-4b5a-9b35-a1e6c1849d3f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251458389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.251458389
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.624371362
Short name T742
Test name
Test status
Simulation time 46742148 ps
CPU time 0.64 seconds
Started Jul 28 05:11:27 PM PDT 24
Finished Jul 28 05:11:28 PM PDT 24
Peak memory 197648 kb
Host smart-5dd77112-fd15-4225-b939-7a042472d316
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624371362 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.624371362
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1444346546
Short name T78
Test name
Test status
Simulation time 39589865 ps
CPU time 0.56 seconds
Started Jul 28 05:11:31 PM PDT 24
Finished Jul 28 05:11:31 PM PDT 24
Peak memory 194840 kb
Host smart-38abbbea-c002-4a39-986a-492b84bceb24
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444346546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1444346546
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1303963876
Short name T761
Test name
Test status
Simulation time 38036903 ps
CPU time 0.59 seconds
Started Jul 28 05:11:20 PM PDT 24
Finished Jul 28 05:11:21 PM PDT 24
Peak memory 193984 kb
Host smart-983cd1f0-e8bc-4cd5-b99a-de6832d5f33b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303963876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1303963876
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.4173243751
Short name T839
Test name
Test status
Simulation time 42950406 ps
CPU time 0.63 seconds
Started Jul 28 05:11:18 PM PDT 24
Finished Jul 28 05:11:18 PM PDT 24
Peak memory 194956 kb
Host smart-1e1bf313-ee35-4b7a-843a-08dda77ba564
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173243751 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.4173243751
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1438342896
Short name T747
Test name
Test status
Simulation time 129560920 ps
CPU time 1.99 seconds
Started Jul 28 05:11:19 PM PDT 24
Finished Jul 28 05:11:22 PM PDT 24
Peak memory 198428 kb
Host smart-7de94630-ab44-4d98-a3a9-e25e99b6c3e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438342896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1438342896
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.374268563
Short name T823
Test name
Test status
Simulation time 58301130 ps
CPU time 0.87 seconds
Started Jul 28 05:11:13 PM PDT 24
Finished Jul 28 05:11:14 PM PDT 24
Peak memory 197296 kb
Host smart-4b0b4c5a-0fbc-4170-9cff-bee26371965a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374268563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.374268563
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3546715225
Short name T836
Test name
Test status
Simulation time 42684571 ps
CPU time 0.58 seconds
Started Jul 28 05:11:28 PM PDT 24
Finished Jul 28 05:11:28 PM PDT 24
Peak memory 193992 kb
Host smart-b515da27-60d4-4cd0-aae9-a993543a85ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546715225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3546715225
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.713970507
Short name T744
Test name
Test status
Simulation time 57341657 ps
CPU time 0.6 seconds
Started Jul 28 05:11:30 PM PDT 24
Finished Jul 28 05:11:30 PM PDT 24
Peak memory 194092 kb
Host smart-07ff43a8-bfaa-4a0d-979f-6d3aeaa84f25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713970507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.713970507
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1326090900
Short name T786
Test name
Test status
Simulation time 78789089 ps
CPU time 0.62 seconds
Started Jul 28 05:11:41 PM PDT 24
Finished Jul 28 05:11:42 PM PDT 24
Peak memory 194788 kb
Host smart-0a1c81d6-aa30-4b94-bbdd-2ae6b1aa283b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326090900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1326090900
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.2982256920
Short name T830
Test name
Test status
Simulation time 15753379 ps
CPU time 0.57 seconds
Started Jul 28 05:11:31 PM PDT 24
Finished Jul 28 05:11:32 PM PDT 24
Peak memory 194076 kb
Host smart-5fb911e1-ed41-4234-ac12-467613165025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982256920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.2982256920
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3093618717
Short name T795
Test name
Test status
Simulation time 45711222 ps
CPU time 0.65 seconds
Started Jul 28 05:11:38 PM PDT 24
Finished Jul 28 05:11:39 PM PDT 24
Peak memory 194096 kb
Host smart-13415047-31a0-4fab-b2c3-706b5ffa312e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093618717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3093618717
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1280014156
Short name T781
Test name
Test status
Simulation time 14377524 ps
CPU time 0.56 seconds
Started Jul 28 05:11:42 PM PDT 24
Finished Jul 28 05:11:43 PM PDT 24
Peak memory 194032 kb
Host smart-9e01c44c-56f0-40db-add8-da5210cd3c44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280014156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1280014156
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.241485405
Short name T790
Test name
Test status
Simulation time 17543178 ps
CPU time 0.6 seconds
Started Jul 28 05:11:45 PM PDT 24
Finished Jul 28 05:11:46 PM PDT 24
Peak memory 194000 kb
Host smart-14ec04f5-09f6-4fa3-92cc-62187a90b8c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241485405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.241485405
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.3720726523
Short name T784
Test name
Test status
Simulation time 58123841 ps
CPU time 0.6 seconds
Started Jul 28 05:11:37 PM PDT 24
Finished Jul 28 05:11:37 PM PDT 24
Peak memory 194132 kb
Host smart-228a95a9-c1b9-4d64-a867-efe1560ffb8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720726523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3720726523
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1304961820
Short name T749
Test name
Test status
Simulation time 55538950 ps
CPU time 0.59 seconds
Started Jul 28 05:11:39 PM PDT 24
Finished Jul 28 05:11:40 PM PDT 24
Peak memory 194024 kb
Host smart-6fde79b0-a5f0-4ad9-8f77-0beb58325678
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304961820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1304961820
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.4002238274
Short name T719
Test name
Test status
Simulation time 35721891 ps
CPU time 0.56 seconds
Started Jul 28 05:11:40 PM PDT 24
Finished Jul 28 05:11:41 PM PDT 24
Peak memory 194048 kb
Host smart-8962b563-c427-481d-b4f4-b72092d9352f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002238274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.4002238274
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1783757042
Short name T752
Test name
Test status
Simulation time 20337261 ps
CPU time 0.63 seconds
Started Jul 28 05:11:34 PM PDT 24
Finished Jul 28 05:11:34 PM PDT 24
Peak memory 195136 kb
Host smart-1b9b25ea-38cf-4c97-9441-fbcee24a32ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783757042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1783757042
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.4276638099
Short name T824
Test name
Test status
Simulation time 1144256216 ps
CPU time 3.05 seconds
Started Jul 28 05:11:24 PM PDT 24
Finished Jul 28 05:11:27 PM PDT 24
Peak memory 197340 kb
Host smart-dc15fd83-d717-4039-981e-558d0b11fea3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276638099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.4276638099
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.52877968
Short name T818
Test name
Test status
Simulation time 20286491 ps
CPU time 0.65 seconds
Started Jul 28 05:11:20 PM PDT 24
Finished Jul 28 05:11:20 PM PDT 24
Peak memory 195256 kb
Host smart-02198eac-b99a-4026-bc63-e443b7b62573
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52877968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.52877968
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.4290946906
Short name T735
Test name
Test status
Simulation time 326026615 ps
CPU time 2.14 seconds
Started Jul 28 05:11:16 PM PDT 24
Finished Jul 28 05:11:19 PM PDT 24
Peak memory 198404 kb
Host smart-8fe0699d-5beb-447c-90e6-4a9d51b752cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290946906 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.4290946906
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.598899726
Short name T66
Test name
Test status
Simulation time 63655175 ps
CPU time 0.63 seconds
Started Jul 28 05:11:26 PM PDT 24
Finished Jul 28 05:11:26 PM PDT 24
Peak memory 195204 kb
Host smart-01e8ad68-d507-4c98-81f2-10d16d57e339
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598899726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_
csr_rw.598899726
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1676213380
Short name T728
Test name
Test status
Simulation time 35766466 ps
CPU time 0.56 seconds
Started Jul 28 05:11:27 PM PDT 24
Finished Jul 28 05:11:27 PM PDT 24
Peak memory 194672 kb
Host smart-11fd8860-3a6c-4819-af7e-574a2c5a88b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676213380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1676213380
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2161232527
Short name T56
Test name
Test status
Simulation time 116994404 ps
CPU time 0.71 seconds
Started Jul 28 05:11:19 PM PDT 24
Finished Jul 28 05:11:25 PM PDT 24
Peak memory 195460 kb
Host smart-558331aa-474f-4491-a8e4-32ebe10dede1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161232527 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.2161232527
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.562937864
Short name T814
Test name
Test status
Simulation time 111754346 ps
CPU time 2.06 seconds
Started Jul 28 05:11:19 PM PDT 24
Finished Jul 28 05:11:21 PM PDT 24
Peak memory 198348 kb
Host smart-e1c7347a-cf24-45c4-a387-b25bbfd15243
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562937864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.562937864
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.847650721
Short name T822
Test name
Test status
Simulation time 368833113 ps
CPU time 1.14 seconds
Started Jul 28 05:11:36 PM PDT 24
Finished Jul 28 05:11:37 PM PDT 24
Peak memory 198304 kb
Host smart-0f2633d4-83a5-4981-b1dd-1f0f13ab1311
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847650721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.847650721
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.3677136559
Short name T783
Test name
Test status
Simulation time 17508701 ps
CPU time 0.68 seconds
Started Jul 28 05:12:08 PM PDT 24
Finished Jul 28 05:12:09 PM PDT 24
Peak memory 194164 kb
Host smart-b7946c7f-8440-4916-be59-ef6b3b46465d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677136559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3677136559
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1095315725
Short name T826
Test name
Test status
Simulation time 14358948 ps
CPU time 0.59 seconds
Started Jul 28 05:11:39 PM PDT 24
Finished Jul 28 05:11:39 PM PDT 24
Peak memory 193968 kb
Host smart-a7c7e64d-e844-4aca-be23-9ef7c91a56d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095315725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1095315725
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3313435301
Short name T770
Test name
Test status
Simulation time 31979876 ps
CPU time 0.57 seconds
Started Jul 28 05:11:35 PM PDT 24
Finished Jul 28 05:11:35 PM PDT 24
Peak memory 194032 kb
Host smart-e62b0a9a-f36f-45c8-941c-ab03a9ad2f15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313435301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3313435301
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.2746541969
Short name T829
Test name
Test status
Simulation time 16946835 ps
CPU time 0.65 seconds
Started Jul 28 05:11:47 PM PDT 24
Finished Jul 28 05:11:48 PM PDT 24
Peak memory 194716 kb
Host smart-5a99142f-9718-43e1-8aa9-a5197e86f71b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746541969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2746541969
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1840199239
Short name T811
Test name
Test status
Simulation time 52034206 ps
CPU time 0.61 seconds
Started Jul 28 05:11:37 PM PDT 24
Finished Jul 28 05:11:38 PM PDT 24
Peak memory 194116 kb
Host smart-d17814b3-1cec-4c77-9757-be337586ca01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840199239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1840199239
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3707246366
Short name T746
Test name
Test status
Simulation time 16210115 ps
CPU time 0.57 seconds
Started Jul 28 05:11:41 PM PDT 24
Finished Jul 28 05:11:42 PM PDT 24
Peak memory 194084 kb
Host smart-43ac832f-3390-49ac-bf82-746ae1dd74b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707246366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3707246366
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2034770460
Short name T745
Test name
Test status
Simulation time 20919288 ps
CPU time 0.58 seconds
Started Jul 28 05:11:37 PM PDT 24
Finished Jul 28 05:11:38 PM PDT 24
Peak memory 194032 kb
Host smart-40cf6a66-26df-4eb6-8c48-9076d1992359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034770460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2034770460
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3299341942
Short name T727
Test name
Test status
Simulation time 46152731 ps
CPU time 0.63 seconds
Started Jul 28 05:11:40 PM PDT 24
Finished Jul 28 05:11:41 PM PDT 24
Peak memory 194600 kb
Host smart-82ce2ae2-38cd-4583-a0ee-8ecf7d9be839
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299341942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3299341942
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2172288583
Short name T835
Test name
Test status
Simulation time 14157232 ps
CPU time 0.58 seconds
Started Jul 28 05:11:31 PM PDT 24
Finished Jul 28 05:11:32 PM PDT 24
Peak memory 193904 kb
Host smart-9b63b27a-e5b3-40e4-a80a-6564ae67479a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172288583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2172288583
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3511689168
Short name T733
Test name
Test status
Simulation time 69461938 ps
CPU time 0.6 seconds
Started Jul 28 05:11:31 PM PDT 24
Finished Jul 28 05:11:32 PM PDT 24
Peak memory 194080 kb
Host smart-c1e7ec01-5ffa-40b6-b036-483349e3b121
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511689168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3511689168
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2887255221
Short name T832
Test name
Test status
Simulation time 26876567 ps
CPU time 0.66 seconds
Started Jul 28 05:11:29 PM PDT 24
Finished Jul 28 05:11:29 PM PDT 24
Peak memory 194808 kb
Host smart-0b772136-f373-4546-a2a5-0dc11657c00f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887255221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2887255221
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1925407899
Short name T754
Test name
Test status
Simulation time 37373067 ps
CPU time 1.33 seconds
Started Jul 28 05:11:31 PM PDT 24
Finished Jul 28 05:11:32 PM PDT 24
Peak memory 197296 kb
Host smart-2e7bec78-7ed7-42dd-ad03-c203a21907dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925407899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1925407899
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.830114211
Short name T65
Test name
Test status
Simulation time 106814731 ps
CPU time 0.58 seconds
Started Jul 28 05:11:32 PM PDT 24
Finished Jul 28 05:11:33 PM PDT 24
Peak memory 194576 kb
Host smart-491bd040-1f16-475d-b2e3-3075479c8be3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830114211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.830114211
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1789067549
Short name T743
Test name
Test status
Simulation time 81415022 ps
CPU time 0.74 seconds
Started Jul 28 05:11:16 PM PDT 24
Finished Jul 28 05:11:17 PM PDT 24
Peak memory 198168 kb
Host smart-b67c8f87-2508-449f-bcf9-5c37787b5a47
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789067549 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1789067549
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1812960343
Short name T59
Test name
Test status
Simulation time 33834201 ps
CPU time 0.59 seconds
Started Jul 28 05:11:22 PM PDT 24
Finished Jul 28 05:11:22 PM PDT 24
Peak memory 195164 kb
Host smart-211d2e03-7de5-4955-aef8-ba7bff6943ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812960343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1812960343
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.2753624015
Short name T758
Test name
Test status
Simulation time 16566644 ps
CPU time 0.59 seconds
Started Jul 28 05:11:41 PM PDT 24
Finished Jul 28 05:11:42 PM PDT 24
Peak memory 194008 kb
Host smart-83512c92-7954-4607-aada-c80594cc4335
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753624015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2753624015
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.4003127836
Short name T79
Test name
Test status
Simulation time 22009349 ps
CPU time 0.83 seconds
Started Jul 28 05:11:20 PM PDT 24
Finished Jul 28 05:11:26 PM PDT 24
Peak memory 196752 kb
Host smart-8db1508a-2dd6-4387-8a28-ca4f752f490b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003127836 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.4003127836
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3015576104
Short name T739
Test name
Test status
Simulation time 208096689 ps
CPU time 1.04 seconds
Started Jul 28 05:11:46 PM PDT 24
Finished Jul 28 05:11:47 PM PDT 24
Peak memory 198164 kb
Host smart-dae81894-0ddb-4f9b-9f7d-cc7fcc9261cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015576104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3015576104
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1378139898
Short name T767
Test name
Test status
Simulation time 132217638 ps
CPU time 1.06 seconds
Started Jul 28 05:11:18 PM PDT 24
Finished Jul 28 05:11:25 PM PDT 24
Peak memory 198432 kb
Host smart-4cb6427e-2a7c-4793-8933-64df039ab746
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378139898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1378139898
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2061907540
Short name T789
Test name
Test status
Simulation time 127985159 ps
CPU time 0.58 seconds
Started Jul 28 05:11:36 PM PDT 24
Finished Jul 28 05:11:37 PM PDT 24
Peak memory 194064 kb
Host smart-99c91d55-616c-4a38-90d2-854b2560412a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061907540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2061907540
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2981721046
Short name T724
Test name
Test status
Simulation time 24031485 ps
CPU time 0.6 seconds
Started Jul 28 05:11:38 PM PDT 24
Finished Jul 28 05:11:39 PM PDT 24
Peak memory 194740 kb
Host smart-7423dc24-9d43-4bc1-9a96-5851ec955253
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981721046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2981721046
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3115258548
Short name T721
Test name
Test status
Simulation time 21987398 ps
CPU time 0.58 seconds
Started Jul 28 05:11:41 PM PDT 24
Finished Jul 28 05:11:42 PM PDT 24
Peak memory 194636 kb
Host smart-d49b0ad5-6cd6-495c-9856-c8303de3e635
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115258548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3115258548
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2059397325
Short name T782
Test name
Test status
Simulation time 17077730 ps
CPU time 0.62 seconds
Started Jul 28 05:11:36 PM PDT 24
Finished Jul 28 05:11:37 PM PDT 24
Peak memory 194684 kb
Host smart-35f1252b-8498-44de-8e77-eaf2a79cca7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059397325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2059397325
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1855740941
Short name T755
Test name
Test status
Simulation time 40325966 ps
CPU time 0.59 seconds
Started Jul 28 05:11:52 PM PDT 24
Finished Jul 28 05:11:52 PM PDT 24
Peak memory 194076 kb
Host smart-3cc97309-42e4-4717-be90-12f217486fc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855740941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1855740941
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.96649855
Short name T805
Test name
Test status
Simulation time 47812456 ps
CPU time 0.58 seconds
Started Jul 28 05:11:33 PM PDT 24
Finished Jul 28 05:11:33 PM PDT 24
Peak memory 194728 kb
Host smart-73ccb735-cc42-4320-bf22-ac3c638fd3da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96649855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.96649855
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.3852232094
Short name T748
Test name
Test status
Simulation time 17877764 ps
CPU time 0.62 seconds
Started Jul 28 05:11:35 PM PDT 24
Finished Jul 28 05:11:36 PM PDT 24
Peak memory 194120 kb
Host smart-4aa63354-3249-4424-b4e5-5bf638a5b51e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852232094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.3852232094
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.4245170994
Short name T792
Test name
Test status
Simulation time 13581231 ps
CPU time 0.55 seconds
Started Jul 28 05:11:41 PM PDT 24
Finished Jul 28 05:11:42 PM PDT 24
Peak memory 194052 kb
Host smart-f08c8730-5af0-4588-a324-e5b505c30f4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245170994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.4245170994
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2188344524
Short name T799
Test name
Test status
Simulation time 14384658 ps
CPU time 0.61 seconds
Started Jul 28 05:11:41 PM PDT 24
Finished Jul 28 05:11:42 PM PDT 24
Peak memory 194040 kb
Host smart-ac931b7b-1e3f-42fb-a512-c585f1e34bb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188344524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2188344524
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2029901106
Short name T804
Test name
Test status
Simulation time 25107188 ps
CPU time 0.61 seconds
Started Jul 28 05:11:37 PM PDT 24
Finished Jul 28 05:11:38 PM PDT 24
Peak memory 194132 kb
Host smart-0e978ab2-4435-47ed-953c-66ba895f3f55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029901106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2029901106
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.778672163
Short name T780
Test name
Test status
Simulation time 17172658 ps
CPU time 0.79 seconds
Started Jul 28 05:11:20 PM PDT 24
Finished Jul 28 05:11:20 PM PDT 24
Peak memory 198164 kb
Host smart-b18cafb1-7be5-47c6-8d33-2b0bea0c76f1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778672163 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.778672163
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2265867301
Short name T68
Test name
Test status
Simulation time 12574226 ps
CPU time 0.55 seconds
Started Jul 28 05:11:18 PM PDT 24
Finished Jul 28 05:11:19 PM PDT 24
Peak memory 195044 kb
Host smart-bc59126e-5e7e-457e-9292-d83679217db0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265867301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.2265867301
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3811523666
Short name T806
Test name
Test status
Simulation time 40967138 ps
CPU time 0.58 seconds
Started Jul 28 05:11:28 PM PDT 24
Finished Jul 28 05:11:28 PM PDT 24
Peak memory 193940 kb
Host smart-df82073e-c455-43b7-bcd7-3218585f9764
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811523666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3811523666
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.4239818685
Short name T842
Test name
Test status
Simulation time 143151121 ps
CPU time 0.88 seconds
Started Jul 28 05:11:22 PM PDT 24
Finished Jul 28 05:11:23 PM PDT 24
Peak memory 197432 kb
Host smart-39d2f90b-13bd-4f51-a890-7a599f3cf333
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239818685 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.4239818685
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2641880372
Short name T779
Test name
Test status
Simulation time 217660748 ps
CPU time 2.42 seconds
Started Jul 28 05:11:25 PM PDT 24
Finished Jul 28 05:11:27 PM PDT 24
Peak memory 198348 kb
Host smart-7646e8e3-1a69-4216-a322-07213014dc30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641880372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2641880372
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2523899542
Short name T726
Test name
Test status
Simulation time 22547719 ps
CPU time 1.07 seconds
Started Jul 28 05:11:38 PM PDT 24
Finished Jul 28 05:11:39 PM PDT 24
Peak memory 198344 kb
Host smart-09116403-cc39-40c8-baeb-671c56278923
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523899542 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2523899542
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.283663638
Short name T773
Test name
Test status
Simulation time 11775984 ps
CPU time 0.56 seconds
Started Jul 28 05:11:25 PM PDT 24
Finished Jul 28 05:11:26 PM PDT 24
Peak memory 195572 kb
Host smart-a149eeed-2fee-4f7a-b210-50e2acabb140
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283663638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.283663638
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2350212187
Short name T813
Test name
Test status
Simulation time 57736347 ps
CPU time 0.61 seconds
Started Jul 28 05:11:22 PM PDT 24
Finished Jul 28 05:11:23 PM PDT 24
Peak memory 194116 kb
Host smart-43373e8a-8af9-4d4f-b649-6a5d1f1aa778
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350212187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2350212187
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.810465731
Short name T58
Test name
Test status
Simulation time 27075758 ps
CPU time 0.71 seconds
Started Jul 28 05:11:38 PM PDT 24
Finished Jul 28 05:11:39 PM PDT 24
Peak memory 196084 kb
Host smart-113e4c61-3b71-432f-bfc0-38dcd75dd353
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810465731 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.810465731
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.4130082127
Short name T720
Test name
Test status
Simulation time 65081767 ps
CPU time 1.3 seconds
Started Jul 28 05:11:33 PM PDT 24
Finished Jul 28 05:11:35 PM PDT 24
Peak memory 198296 kb
Host smart-8b6faab8-9a57-49f1-a387-7e16d05cfe06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130082127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.4130082127
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1309270078
Short name T772
Test name
Test status
Simulation time 152398405 ps
CPU time 0.87 seconds
Started Jul 28 05:11:30 PM PDT 24
Finished Jul 28 05:11:31 PM PDT 24
Peak memory 198168 kb
Host smart-9c351433-887a-41cd-8a76-57c956dfe7cc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309270078 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1309270078
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1263564106
Short name T797
Test name
Test status
Simulation time 13528159 ps
CPU time 0.56 seconds
Started Jul 28 05:11:22 PM PDT 24
Finished Jul 28 05:11:22 PM PDT 24
Peak memory 194600 kb
Host smart-5ed1cdcb-ea03-4499-a91d-6aee499deede
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263564106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1263564106
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.4028194197
Short name T816
Test name
Test status
Simulation time 95869368 ps
CPU time 0.73 seconds
Started Jul 28 05:11:32 PM PDT 24
Finished Jul 28 05:11:32 PM PDT 24
Peak memory 196080 kb
Host smart-1a15c2c6-3992-4bbd-9127-9e1ea859acc4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028194197 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.4028194197
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.706515666
Short name T757
Test name
Test status
Simulation time 70128891 ps
CPU time 1.16 seconds
Started Jul 28 05:11:21 PM PDT 24
Finished Jul 28 05:11:23 PM PDT 24
Peak memory 198316 kb
Host smart-56fa8539-b2be-454e-9545-7158e9eef6a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706515666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.706515666
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3618064799
Short name T94
Test name
Test status
Simulation time 652738042 ps
CPU time 1.37 seconds
Started Jul 28 05:11:29 PM PDT 24
Finished Jul 28 05:11:30 PM PDT 24
Peak memory 198356 kb
Host smart-f55348d5-feda-4ebc-84e0-34e30da13c21
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618064799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3618064799
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1275285194
Short name T812
Test name
Test status
Simulation time 32713312 ps
CPU time 0.83 seconds
Started Jul 28 05:11:31 PM PDT 24
Finished Jul 28 05:11:32 PM PDT 24
Peak memory 198156 kb
Host smart-96c15ff4-bfe6-42a2-8f1d-62eabb3d674a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275285194 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.1275285194
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3356757572
Short name T70
Test name
Test status
Simulation time 18663326 ps
CPU time 0.63 seconds
Started Jul 28 05:11:21 PM PDT 24
Finished Jul 28 05:11:22 PM PDT 24
Peak memory 195112 kb
Host smart-d4da47cd-e346-476f-88be-2599871c4fd6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356757572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3356757572
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3426116313
Short name T796
Test name
Test status
Simulation time 26404739 ps
CPU time 0.6 seconds
Started Jul 28 05:11:33 PM PDT 24
Finished Jul 28 05:11:33 PM PDT 24
Peak memory 193996 kb
Host smart-0083d295-384f-4db7-9505-240b447153ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426116313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3426116313
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1043763122
Short name T775
Test name
Test status
Simulation time 65045781 ps
CPU time 0.83 seconds
Started Jul 28 05:11:32 PM PDT 24
Finished Jul 28 05:11:38 PM PDT 24
Peak memory 196524 kb
Host smart-7d0a03f3-ce70-4665-8802-5d1707558e2d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043763122 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1043763122
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1424123399
Short name T736
Test name
Test status
Simulation time 204220226 ps
CPU time 2.26 seconds
Started Jul 28 05:11:19 PM PDT 24
Finished Jul 28 05:11:22 PM PDT 24
Peak memory 198392 kb
Host smart-aa31658a-73c2-440a-a88a-6bd03b4c06b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424123399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1424123399
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2783178738
Short name T31
Test name
Test status
Simulation time 280315287 ps
CPU time 1.12 seconds
Started Jul 28 05:11:27 PM PDT 24
Finished Jul 28 05:11:29 PM PDT 24
Peak memory 198400 kb
Host smart-ae6c4352-0a45-4ddf-90fb-3160e0735baa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783178738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2783178738
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1547763700
Short name T827
Test name
Test status
Simulation time 45449128 ps
CPU time 0.75 seconds
Started Jul 28 05:11:13 PM PDT 24
Finished Jul 28 05:11:14 PM PDT 24
Peak memory 198136 kb
Host smart-5b968026-8c77-41f3-b7c0-ddc2466de1be
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547763700 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1547763700
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3234569085
Short name T810
Test name
Test status
Simulation time 33230017 ps
CPU time 0.56 seconds
Started Jul 28 05:11:31 PM PDT 24
Finished Jul 28 05:11:32 PM PDT 24
Peak memory 194904 kb
Host smart-5c956a73-c839-4920-9ebc-15f8fdb77dc5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234569085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3234569085
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.702940194
Short name T771
Test name
Test status
Simulation time 16255758 ps
CPU time 0.65 seconds
Started Jul 28 05:11:34 PM PDT 24
Finished Jul 28 05:11:34 PM PDT 24
Peak memory 194076 kb
Host smart-e63294c9-6234-4743-bcf6-cdef30b687e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702940194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.702940194
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.576715945
Short name T834
Test name
Test status
Simulation time 38889750 ps
CPU time 0.71 seconds
Started Jul 28 05:11:32 PM PDT 24
Finished Jul 28 05:11:38 PM PDT 24
Peak memory 195268 kb
Host smart-9893684b-55ed-4e97-97bd-0a97d38a440e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576715945 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 9.gpio_same_csr_outstanding.576715945
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1959751507
Short name T841
Test name
Test status
Simulation time 271679069 ps
CPU time 2.21 seconds
Started Jul 28 05:11:54 PM PDT 24
Finished Jul 28 05:11:57 PM PDT 24
Peak memory 198320 kb
Host smart-defa914a-8bcc-4cec-a4ec-1a2539841e0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959751507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1959751507
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.48376179
Short name T38
Test name
Test status
Simulation time 141098931 ps
CPU time 1.14 seconds
Started Jul 28 05:11:28 PM PDT 24
Finished Jul 28 05:11:30 PM PDT 24
Peak memory 198356 kb
Host smart-0e99d8ff-9abb-49a8-abab-fe7510cad9a8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48376179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
9.gpio_tl_intg_err.48376179
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.4103499714
Short name T314
Test name
Test status
Simulation time 19588725 ps
CPU time 0.56 seconds
Started Jul 28 05:13:28 PM PDT 24
Finished Jul 28 05:13:29 PM PDT 24
Peak memory 194592 kb
Host smart-0fa07a70-5927-46d2-ae1b-7404a565f291
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103499714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.4103499714
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2710987635
Short name T492
Test name
Test status
Simulation time 84902664 ps
CPU time 0.78 seconds
Started Jul 28 05:13:25 PM PDT 24
Finished Jul 28 05:13:26 PM PDT 24
Peak memory 196292 kb
Host smart-f88823b9-28d9-4542-bb0f-fc53ae790d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710987635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2710987635
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.1113160419
Short name T313
Test name
Test status
Simulation time 1557372984 ps
CPU time 22.39 seconds
Started Jul 28 05:13:28 PM PDT 24
Finished Jul 28 05:13:51 PM PDT 24
Peak memory 196748 kb
Host smart-d6c63e0c-cf66-4634-87ba-026da320cfd1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113160419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.1113160419
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2804584064
Short name T6
Test name
Test status
Simulation time 119845567 ps
CPU time 0.91 seconds
Started Jul 28 05:13:40 PM PDT 24
Finished Jul 28 05:13:41 PM PDT 24
Peak memory 198120 kb
Host smart-9f38281d-f117-49d5-bd8d-60c377d0f19e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804584064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2804584064
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.830653781
Short name T593
Test name
Test status
Simulation time 163649156 ps
CPU time 1.27 seconds
Started Jul 28 05:13:27 PM PDT 24
Finished Jul 28 05:13:29 PM PDT 24
Peak memory 198532 kb
Host smart-74932cd5-9cff-4f69-b2b9-b17a5387dd48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830653781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.830653781
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3281845621
Short name T354
Test name
Test status
Simulation time 241860301 ps
CPU time 2.53 seconds
Started Jul 28 05:13:27 PM PDT 24
Finished Jul 28 05:13:29 PM PDT 24
Peak memory 198504 kb
Host smart-44fe88f0-295f-47c0-bf63-5e82963fa004
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281845621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3281845621
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.3970022882
Short name T250
Test name
Test status
Simulation time 65381873 ps
CPU time 1.91 seconds
Started Jul 28 05:13:31 PM PDT 24
Finished Jul 28 05:13:33 PM PDT 24
Peak memory 197900 kb
Host smart-45fda8ca-d522-4e05-96e7-d6e5e646db9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970022882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
3970022882
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2437517672
Short name T455
Test name
Test status
Simulation time 66472870 ps
CPU time 0.84 seconds
Started Jul 28 05:13:25 PM PDT 24
Finished Jul 28 05:13:26 PM PDT 24
Peak memory 196848 kb
Host smart-fc45181d-1bea-4124-9a27-7a1f91a0e17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437517672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2437517672
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.477467461
Short name T178
Test name
Test status
Simulation time 114502354 ps
CPU time 1.2 seconds
Started Jul 28 05:13:31 PM PDT 24
Finished Jul 28 05:13:38 PM PDT 24
Peak memory 197732 kb
Host smart-696242eb-3370-413a-bab4-c3b84a9b29e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477467461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.477467461
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2293034481
Short name T643
Test name
Test status
Simulation time 652857301 ps
CPU time 2.47 seconds
Started Jul 28 05:13:35 PM PDT 24
Finished Jul 28 05:13:38 PM PDT 24
Peak memory 198412 kb
Host smart-20647b77-086e-46a5-9c35-556e80001f50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293034481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2293034481
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3384383953
Short name T33
Test name
Test status
Simulation time 90589245 ps
CPU time 0.78 seconds
Started Jul 28 05:13:39 PM PDT 24
Finished Jul 28 05:13:40 PM PDT 24
Peak memory 214340 kb
Host smart-b6b65fd2-d9ac-40c3-8592-21cd908e3023
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384383953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3384383953
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.675173622
Short name T522
Test name
Test status
Simulation time 39737872 ps
CPU time 0.98 seconds
Started Jul 28 05:13:25 PM PDT 24
Finished Jul 28 05:13:26 PM PDT 24
Peak memory 196244 kb
Host smart-cef91c7b-84b1-47ff-a042-2136e9832bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675173622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.675173622
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.786093432
Short name T610
Test name
Test status
Simulation time 36191097 ps
CPU time 0.89 seconds
Started Jul 28 05:13:27 PM PDT 24
Finished Jul 28 05:13:29 PM PDT 24
Peak memory 196052 kb
Host smart-c06a9c9b-3989-4fe1-9362-87e1aedd6cd2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786093432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.786093432
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.2830944881
Short name T244
Test name
Test status
Simulation time 10782258152 ps
CPU time 145.14 seconds
Started Jul 28 05:13:34 PM PDT 24
Finished Jul 28 05:16:00 PM PDT 24
Peak memory 198816 kb
Host smart-ed7eb021-8ef5-4743-af96-94f5676ca373
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830944881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.2830944881
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.1166547244
Short name T92
Test name
Test status
Simulation time 159972011866 ps
CPU time 2038.04 seconds
Started Jul 28 05:13:29 PM PDT 24
Finished Jul 28 05:47:28 PM PDT 24
Peak memory 198732 kb
Host smart-e9bac7eb-8005-4a98-bcbf-b5ccdff20644
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1166547244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.1166547244
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.926298329
Short name T461
Test name
Test status
Simulation time 45130752 ps
CPU time 0.57 seconds
Started Jul 28 05:13:30 PM PDT 24
Finished Jul 28 05:13:31 PM PDT 24
Peak memory 194308 kb
Host smart-b080bc0c-3245-481c-b47e-d631929da938
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926298329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.926298329
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.588050719
Short name T589
Test name
Test status
Simulation time 88239347 ps
CPU time 0.94 seconds
Started Jul 28 05:13:30 PM PDT 24
Finished Jul 28 05:13:31 PM PDT 24
Peak memory 197152 kb
Host smart-eeca92ac-a560-4318-a61e-45d245227952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588050719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.588050719
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1911330098
Short name T266
Test name
Test status
Simulation time 890768218 ps
CPU time 20.65 seconds
Started Jul 28 05:13:33 PM PDT 24
Finished Jul 28 05:13:54 PM PDT 24
Peak memory 196960 kb
Host smart-d2b2d878-b1fb-4207-8142-b7f8f37b10ff
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911330098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1911330098
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2818566402
Short name T692
Test name
Test status
Simulation time 156375075 ps
CPU time 0.9 seconds
Started Jul 28 05:13:29 PM PDT 24
Finished Jul 28 05:13:31 PM PDT 24
Peak memory 198052 kb
Host smart-9f7d5c45-d845-4c05-b5f1-79b264c56853
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818566402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2818566402
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.2845683544
Short name T134
Test name
Test status
Simulation time 354015465 ps
CPU time 1.05 seconds
Started Jul 28 05:13:29 PM PDT 24
Finished Jul 28 05:13:30 PM PDT 24
Peak memory 196316 kb
Host smart-9f74dcd9-8d77-45b9-8e43-18174554e208
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845683544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.2845683544
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.3956060234
Short name T431
Test name
Test status
Simulation time 684419111 ps
CPU time 2.97 seconds
Started Jul 28 05:13:32 PM PDT 24
Finished Jul 28 05:13:35 PM PDT 24
Peak memory 197796 kb
Host smart-42ab7e8b-2f2c-40d6-8ec5-85ba423a4afc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956060234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
3956060234
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.1809278645
Short name T140
Test name
Test status
Simulation time 109033788 ps
CPU time 1.06 seconds
Started Jul 28 05:13:27 PM PDT 24
Finished Jul 28 05:13:28 PM PDT 24
Peak memory 197064 kb
Host smart-9c8fe08e-96b4-4e8a-a8a0-5b6253818bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809278645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.1809278645
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2654683106
Short name T391
Test name
Test status
Simulation time 20123542 ps
CPU time 0.65 seconds
Started Jul 28 05:13:30 PM PDT 24
Finished Jul 28 05:13:31 PM PDT 24
Peak memory 194708 kb
Host smart-9f0443ec-2e5c-49e7-930b-94a0b49f122c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654683106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2654683106
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1936303190
Short name T112
Test name
Test status
Simulation time 1019458738 ps
CPU time 3.48 seconds
Started Jul 28 05:13:28 PM PDT 24
Finished Jul 28 05:13:32 PM PDT 24
Peak memory 198536 kb
Host smart-4b48e7c6-8bc5-460e-898f-8a47798a6b0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936303190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.1936303190
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.960213517
Short name T45
Test name
Test status
Simulation time 36516855 ps
CPU time 0.79 seconds
Started Jul 28 05:13:28 PM PDT 24
Finished Jul 28 05:13:29 PM PDT 24
Peak memory 214400 kb
Host smart-e46a1571-c5c1-4e30-9f8d-cacf3c009546
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960213517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.960213517
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.3540543889
Short name T546
Test name
Test status
Simulation time 216340305 ps
CPU time 1.36 seconds
Started Jul 28 05:13:39 PM PDT 24
Finished Jul 28 05:13:41 PM PDT 24
Peak memory 196968 kb
Host smart-80a9135c-8e16-47a0-ac5e-7639da8379bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540543889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3540543889
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1415414940
Short name T172
Test name
Test status
Simulation time 167493660 ps
CPU time 0.84 seconds
Started Jul 28 05:13:44 PM PDT 24
Finished Jul 28 05:13:45 PM PDT 24
Peak memory 195556 kb
Host smart-eddf4024-bb5f-4e03-b768-2e33baed4947
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415414940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1415414940
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.2645725759
Short name T439
Test name
Test status
Simulation time 20498610419 ps
CPU time 66.62 seconds
Started Jul 28 05:13:31 PM PDT 24
Finished Jul 28 05:14:38 PM PDT 24
Peak memory 198588 kb
Host smart-df931382-3210-4239-b315-e47aa37ff85a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645725759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2645725759
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2530234032
Short name T261
Test name
Test status
Simulation time 42379750 ps
CPU time 0.56 seconds
Started Jul 28 05:13:39 PM PDT 24
Finished Jul 28 05:13:40 PM PDT 24
Peak memory 194452 kb
Host smart-78c835e5-0f6c-4874-aa8b-59132d8333e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530234032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2530234032
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2164587286
Short name T246
Test name
Test status
Simulation time 23162832 ps
CPU time 0.81 seconds
Started Jul 28 05:13:53 PM PDT 24
Finished Jul 28 05:13:54 PM PDT 24
Peak memory 196512 kb
Host smart-3277b912-1e68-4132-ad23-58af0bef1fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164587286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2164587286
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1959541682
Short name T550
Test name
Test status
Simulation time 414184509 ps
CPU time 5.74 seconds
Started Jul 28 05:13:58 PM PDT 24
Finished Jul 28 05:14:04 PM PDT 24
Peak memory 197304 kb
Host smart-73798e35-5190-40cf-85fb-eab7d85ab243
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959541682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1959541682
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1741197157
Short name T536
Test name
Test status
Simulation time 166557204 ps
CPU time 1 seconds
Started Jul 28 05:14:02 PM PDT 24
Finished Jul 28 05:14:03 PM PDT 24
Peak memory 196908 kb
Host smart-0ddc86e2-013e-486f-bb4c-ceab6afd4af5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741197157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1741197157
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.1738277117
Short name T155
Test name
Test status
Simulation time 76109258 ps
CPU time 1.15 seconds
Started Jul 28 05:13:42 PM PDT 24
Finished Jul 28 05:13:43 PM PDT 24
Peak memory 197208 kb
Host smart-deae2656-7e41-4105-9759-a745a4094921
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738277117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.1738277117
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2112684932
Short name T714
Test name
Test status
Simulation time 179334777 ps
CPU time 3.65 seconds
Started Jul 28 05:13:57 PM PDT 24
Finished Jul 28 05:14:01 PM PDT 24
Peak memory 198756 kb
Host smart-0b711093-3d29-4b01-988d-475ad5103372
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112684932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2112684932
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1857906510
Short name T309
Test name
Test status
Simulation time 119134399 ps
CPU time 2.69 seconds
Started Jul 28 05:13:53 PM PDT 24
Finished Jul 28 05:13:55 PM PDT 24
Peak memory 197484 kb
Host smart-1f475a8d-41c6-45a9-9778-a2b50690ec0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857906510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1857906510
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.414295111
Short name T529
Test name
Test status
Simulation time 27115943 ps
CPU time 0.97 seconds
Started Jul 28 05:13:49 PM PDT 24
Finished Jul 28 05:13:50 PM PDT 24
Peak memory 197140 kb
Host smart-7a5eefe7-c0f8-4e9b-a9af-f58ed9fc98f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414295111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.414295111
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3030023099
Short name T445
Test name
Test status
Simulation time 23497217 ps
CPU time 0.84 seconds
Started Jul 28 05:13:43 PM PDT 24
Finished Jul 28 05:13:43 PM PDT 24
Peak memory 197116 kb
Host smart-1750295f-1411-4d15-b224-47eeacb7ec35
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030023099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3030023099
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.2171362034
Short name T298
Test name
Test status
Simulation time 296437163 ps
CPU time 3.38 seconds
Started Jul 28 05:13:59 PM PDT 24
Finished Jul 28 05:14:02 PM PDT 24
Peak memory 198504 kb
Host smart-a1c89959-9e43-4e0b-aaa2-584c8e1256b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171362034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.2171362034
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.3593434043
Short name T103
Test name
Test status
Simulation time 91668427 ps
CPU time 1.46 seconds
Started Jul 28 05:13:56 PM PDT 24
Finished Jul 28 05:13:57 PM PDT 24
Peak memory 198388 kb
Host smart-13c90325-0d68-47d7-9d08-c777ac235bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593434043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.3593434043
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2057139417
Short name T568
Test name
Test status
Simulation time 71848439 ps
CPU time 0.9 seconds
Started Jul 28 05:13:36 PM PDT 24
Finished Jul 28 05:13:37 PM PDT 24
Peak memory 196780 kb
Host smart-294407c8-747d-4163-b3f8-fc338ea11850
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057139417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2057139417
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1999545281
Short name T630
Test name
Test status
Simulation time 4811039060 ps
CPU time 112.54 seconds
Started Jul 28 05:13:54 PM PDT 24
Finished Jul 28 05:15:47 PM PDT 24
Peak memory 198588 kb
Host smart-5a47f773-6f0b-471b-96b8-8a741b2739ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999545281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1999545281
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.3712979593
Short name T325
Test name
Test status
Simulation time 155113115671 ps
CPU time 1061.06 seconds
Started Jul 28 05:14:09 PM PDT 24
Finished Jul 28 05:31:50 PM PDT 24
Peak memory 198744 kb
Host smart-e5ec7f28-ed4e-4117-a3b8-0bbd0f1d8643
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3712979593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.3712979593
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.559971711
Short name T165
Test name
Test status
Simulation time 72681659 ps
CPU time 0.58 seconds
Started Jul 28 05:14:01 PM PDT 24
Finished Jul 28 05:14:02 PM PDT 24
Peak memory 196140 kb
Host smart-d4a2c813-36f9-44f4-bb8e-5f0e1c9e7a1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559971711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.559971711
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2380495322
Short name T569
Test name
Test status
Simulation time 29722272 ps
CPU time 0.68 seconds
Started Jul 28 05:13:54 PM PDT 24
Finished Jul 28 05:13:54 PM PDT 24
Peak memory 195552 kb
Host smart-1eb24f3b-563d-4c70-ab65-11a4412d2162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380495322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2380495322
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.3512423507
Short name T634
Test name
Test status
Simulation time 733620707 ps
CPU time 18.87 seconds
Started Jul 28 05:13:48 PM PDT 24
Finished Jul 28 05:14:07 PM PDT 24
Peak memory 198496 kb
Host smart-2f52d833-7b34-46b2-9ad3-9a139e5c6144
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512423507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.3512423507
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3213297802
Short name T469
Test name
Test status
Simulation time 46129887 ps
CPU time 0.89 seconds
Started Jul 28 05:13:47 PM PDT 24
Finished Jul 28 05:13:48 PM PDT 24
Peak memory 197664 kb
Host smart-4d309486-6323-4daf-9869-bef9f36eef4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213297802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3213297802
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3961178070
Short name T115
Test name
Test status
Simulation time 29601496 ps
CPU time 0.74 seconds
Started Jul 28 05:14:02 PM PDT 24
Finished Jul 28 05:14:03 PM PDT 24
Peak memory 195696 kb
Host smart-418d86ee-23a2-46d1-88ee-5e4a615b6bc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961178070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3961178070
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.1437177607
Short name T453
Test name
Test status
Simulation time 86193802 ps
CPU time 3.25 seconds
Started Jul 28 05:14:03 PM PDT 24
Finished Jul 28 05:14:07 PM PDT 24
Peak memory 198524 kb
Host smart-5fa97ae7-cf90-4726-bf0f-3d76fcf6e6a2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437177607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.1437177607
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.117988021
Short name T333
Test name
Test status
Simulation time 156123160 ps
CPU time 1.11 seconds
Started Jul 28 05:13:58 PM PDT 24
Finished Jul 28 05:13:59 PM PDT 24
Peak memory 196024 kb
Host smart-422876d0-4703-4216-a13f-350a8c376292
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117988021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.
117988021
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.845775100
Short name T519
Test name
Test status
Simulation time 37528690 ps
CPU time 1.3 seconds
Started Jul 28 05:14:02 PM PDT 24
Finished Jul 28 05:14:03 PM PDT 24
Peak memory 197492 kb
Host smart-90f3cae5-6668-44a8-a04c-351ab17e286c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845775100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.845775100
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.1570624239
Short name T504
Test name
Test status
Simulation time 64157717 ps
CPU time 1.16 seconds
Started Jul 28 05:13:47 PM PDT 24
Finished Jul 28 05:13:49 PM PDT 24
Peak memory 196316 kb
Host smart-49f2dcce-c67e-41a3-89ca-e4058d403888
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570624239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.1570624239
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2883182315
Short name T533
Test name
Test status
Simulation time 424767283 ps
CPU time 2.8 seconds
Started Jul 28 05:14:02 PM PDT 24
Finished Jul 28 05:14:05 PM PDT 24
Peak memory 198492 kb
Host smart-a5e0b8bc-b609-45ad-89a9-15e98cd7d1df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883182315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2883182315
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1460724632
Short name T598
Test name
Test status
Simulation time 101042030 ps
CPU time 1.33 seconds
Started Jul 28 05:13:44 PM PDT 24
Finished Jul 28 05:13:45 PM PDT 24
Peak memory 197268 kb
Host smart-9dc0be3c-2e3a-4d34-964b-8962124cfa18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460724632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1460724632
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.405183601
Short name T705
Test name
Test status
Simulation time 50651023 ps
CPU time 0.83 seconds
Started Jul 28 05:13:40 PM PDT 24
Finished Jul 28 05:13:41 PM PDT 24
Peak memory 196640 kb
Host smart-7fde2b56-a038-4090-b7f7-0018a0ccf124
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405183601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.405183601
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3141699871
Short name T564
Test name
Test status
Simulation time 1322277006 ps
CPU time 16.51 seconds
Started Jul 28 05:13:59 PM PDT 24
Finished Jul 28 05:14:15 PM PDT 24
Peak memory 198560 kb
Host smart-ab8598be-93ac-484c-8893-961f6e5c7681
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141699871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3141699871
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1564137278
Short name T377
Test name
Test status
Simulation time 17651000 ps
CPU time 0.57 seconds
Started Jul 28 05:13:54 PM PDT 24
Finished Jul 28 05:13:54 PM PDT 24
Peak memory 194456 kb
Host smart-334b9ae2-5f97-4fc5-a7b6-4f89a55bcc46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564137278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1564137278
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2602574140
Short name T423
Test name
Test status
Simulation time 33787175 ps
CPU time 0.8 seconds
Started Jul 28 05:14:00 PM PDT 24
Finished Jul 28 05:14:01 PM PDT 24
Peak memory 195764 kb
Host smart-4efa37d3-aa89-4cc1-96ec-e6a712f0d8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602574140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2602574140
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.1431258443
Short name T149
Test name
Test status
Simulation time 3043640557 ps
CPU time 18.61 seconds
Started Jul 28 05:14:02 PM PDT 24
Finished Jul 28 05:14:21 PM PDT 24
Peak memory 197032 kb
Host smart-fa2c42e8-1122-4f66-a69e-a9a2062e94db
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431258443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.1431258443
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.4242449517
Short name T164
Test name
Test status
Simulation time 132004587 ps
CPU time 0.97 seconds
Started Jul 28 05:13:58 PM PDT 24
Finished Jul 28 05:13:59 PM PDT 24
Peak memory 197068 kb
Host smart-e8bfd283-0e70-40ed-8d97-cc22825725fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242449517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.4242449517
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.123574314
Short name T150
Test name
Test status
Simulation time 173863657 ps
CPU time 0.99 seconds
Started Jul 28 05:14:04 PM PDT 24
Finished Jul 28 05:14:06 PM PDT 24
Peak memory 196448 kb
Host smart-245b866d-fe0c-4196-b097-187d579533b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123574314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.123574314
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1168787508
Short name T703
Test name
Test status
Simulation time 100528483 ps
CPU time 1.97 seconds
Started Jul 28 05:13:59 PM PDT 24
Finished Jul 28 05:14:02 PM PDT 24
Peak memory 196972 kb
Host smart-76b63bfd-1c81-43ea-bada-240440c7ddde
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168787508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1168787508
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1064036719
Short name T211
Test name
Test status
Simulation time 82377210 ps
CPU time 1.89 seconds
Started Jul 28 05:13:51 PM PDT 24
Finished Jul 28 05:13:53 PM PDT 24
Peak memory 196356 kb
Host smart-00dd8cab-9608-406f-b5b3-39bf877d33a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064036719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1064036719
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1635803618
Short name T417
Test name
Test status
Simulation time 76930528 ps
CPU time 0.84 seconds
Started Jul 28 05:13:45 PM PDT 24
Finished Jul 28 05:13:46 PM PDT 24
Peak memory 196404 kb
Host smart-0d7c0828-824c-4716-8d0c-6ec3b1379a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635803618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1635803618
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.779107148
Short name T404
Test name
Test status
Simulation time 33410571 ps
CPU time 1.24 seconds
Started Jul 28 05:13:41 PM PDT 24
Finished Jul 28 05:13:42 PM PDT 24
Peak memory 198424 kb
Host smart-4353799e-3e3b-42a1-b754-496c33039884
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779107148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.779107148
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2359866808
Short name T396
Test name
Test status
Simulation time 145806811 ps
CPU time 1.44 seconds
Started Jul 28 05:13:53 PM PDT 24
Finished Jul 28 05:13:55 PM PDT 24
Peak memory 198444 kb
Host smart-1c0c14b4-69e9-41a0-87c0-179790748d3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359866808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2359866808
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.3073618389
Short name T286
Test name
Test status
Simulation time 137764097 ps
CPU time 1.38 seconds
Started Jul 28 05:13:52 PM PDT 24
Finished Jul 28 05:13:54 PM PDT 24
Peak memory 198452 kb
Host smart-0b27458a-8c44-4ae3-bc48-34a819f928a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073618389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3073618389
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3643609229
Short name T351
Test name
Test status
Simulation time 509458726 ps
CPU time 1.1 seconds
Started Jul 28 05:13:50 PM PDT 24
Finished Jul 28 05:13:51 PM PDT 24
Peak memory 198452 kb
Host smart-fda70b14-4e60-4984-aac2-75544bc6ab36
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643609229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3643609229
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3495349274
Short name T170
Test name
Test status
Simulation time 3022495715 ps
CPU time 78.22 seconds
Started Jul 28 05:14:01 PM PDT 24
Finished Jul 28 05:15:20 PM PDT 24
Peak memory 198612 kb
Host smart-92735b2a-516e-42a4-9f3e-176a16e2075b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495349274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3495349274
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.3379738360
Short name T494
Test name
Test status
Simulation time 181223773627 ps
CPU time 2228.2 seconds
Started Jul 28 05:13:57 PM PDT 24
Finished Jul 28 05:51:06 PM PDT 24
Peak memory 198688 kb
Host smart-5932a573-5fd3-4038-9620-9c7b7197d989
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3379738360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.3379738360
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.402975806
Short name T198
Test name
Test status
Simulation time 124022278 ps
CPU time 0.58 seconds
Started Jul 28 05:13:58 PM PDT 24
Finished Jul 28 05:13:59 PM PDT 24
Peak memory 194592 kb
Host smart-cf49712c-bef1-4d91-866d-e2e195dc6f6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402975806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.402975806
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.931110930
Short name T441
Test name
Test status
Simulation time 45911382 ps
CPU time 0.84 seconds
Started Jul 28 05:14:05 PM PDT 24
Finished Jul 28 05:14:06 PM PDT 24
Peak memory 195936 kb
Host smart-013cf8da-07c7-4a35-892f-54c726b2315b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931110930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.931110930
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.727949757
Short name T147
Test name
Test status
Simulation time 1299221023 ps
CPU time 5.59 seconds
Started Jul 28 05:13:59 PM PDT 24
Finished Jul 28 05:14:05 PM PDT 24
Peak memory 197100 kb
Host smart-ebbb0eec-bca7-43d3-9fc1-ef60b2c81cca
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727949757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.727949757
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2790326115
Short name T641
Test name
Test status
Simulation time 183388496 ps
CPU time 1.04 seconds
Started Jul 28 05:13:45 PM PDT 24
Finished Jul 28 05:13:46 PM PDT 24
Peak memory 196892 kb
Host smart-b55c138a-ae8f-4420-86c4-584aabaf1a11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790326115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2790326115
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.575634315
Short name T473
Test name
Test status
Simulation time 49307584 ps
CPU time 0.95 seconds
Started Jul 28 05:13:55 PM PDT 24
Finished Jul 28 05:13:56 PM PDT 24
Peak memory 197004 kb
Host smart-930cc626-c497-4a5c-8e27-4fe9bd2ebbf3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575634315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.575634315
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.88939143
Short name T465
Test name
Test status
Simulation time 78360278 ps
CPU time 3.25 seconds
Started Jul 28 05:13:57 PM PDT 24
Finished Jul 28 05:14:00 PM PDT 24
Peak memory 198528 kb
Host smart-c1150371-c7ef-4d49-bf05-2e2265029035
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88939143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.gpio_intr_with_filter_rand_intr_event.88939143
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.1071438525
Short name T255
Test name
Test status
Simulation time 254599181 ps
CPU time 2.07 seconds
Started Jul 28 05:13:59 PM PDT 24
Finished Jul 28 05:14:01 PM PDT 24
Peak memory 197416 kb
Host smart-5ca0f182-2f40-4f9f-a203-54fc881727b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071438525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.1071438525
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.3095904370
Short name T218
Test name
Test status
Simulation time 197480451 ps
CPU time 0.98 seconds
Started Jul 28 05:13:57 PM PDT 24
Finished Jul 28 05:13:58 PM PDT 24
Peak memory 197144 kb
Host smart-36b69f92-2274-4b37-ac28-487e16e7f611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095904370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.3095904370
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2959140899
Short name T450
Test name
Test status
Simulation time 57018367 ps
CPU time 1.32 seconds
Started Jul 28 05:13:52 PM PDT 24
Finished Jul 28 05:13:54 PM PDT 24
Peak memory 198504 kb
Host smart-a5575659-3089-4903-ba81-38830421c7dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959140899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2959140899
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3200834966
Short name T501
Test name
Test status
Simulation time 812924427 ps
CPU time 2.69 seconds
Started Jul 28 05:13:55 PM PDT 24
Finished Jul 28 05:13:58 PM PDT 24
Peak memory 198480 kb
Host smart-b04cd195-2087-4ef7-847f-8fddb384039b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200834966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3200834966
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.458451291
Short name T512
Test name
Test status
Simulation time 115056827 ps
CPU time 1.03 seconds
Started Jul 28 05:13:52 PM PDT 24
Finished Jul 28 05:13:53 PM PDT 24
Peak memory 196984 kb
Host smart-a78a0b44-8f7f-4ed8-8477-bc9686fb7e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458451291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.458451291
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.402715500
Short name T310
Test name
Test status
Simulation time 18963422 ps
CPU time 0.68 seconds
Started Jul 28 05:13:47 PM PDT 24
Finished Jul 28 05:13:48 PM PDT 24
Peak memory 194652 kb
Host smart-93411144-f3b7-48b6-b089-bc8fce9aa3e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402715500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.402715500
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.834976426
Short name T646
Test name
Test status
Simulation time 7204028866 ps
CPU time 182.76 seconds
Started Jul 28 05:14:10 PM PDT 24
Finished Jul 28 05:17:13 PM PDT 24
Peak memory 198632 kb
Host smart-06caca14-706d-481a-b2be-781673c46d44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834976426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.834976426
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.3805873932
Short name T543
Test name
Test status
Simulation time 27994559 ps
CPU time 0.59 seconds
Started Jul 28 05:14:04 PM PDT 24
Finished Jul 28 05:14:05 PM PDT 24
Peak memory 195360 kb
Host smart-2809caba-216c-44fd-8ab8-7d7592997b73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805873932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3805873932
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3934069787
Short name T376
Test name
Test status
Simulation time 126835106 ps
CPU time 0.98 seconds
Started Jul 28 05:14:02 PM PDT 24
Finished Jul 28 05:14:03 PM PDT 24
Peak memory 196988 kb
Host smart-70ba3d73-0c4e-4efb-8c98-d06e01d1a039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934069787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3934069787
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2860710050
Short name T416
Test name
Test status
Simulation time 528028528 ps
CPU time 14.86 seconds
Started Jul 28 05:14:00 PM PDT 24
Finished Jul 28 05:14:15 PM PDT 24
Peak memory 197140 kb
Host smart-c8d544e4-a22b-4033-a9fb-363c0281045c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860710050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2860710050
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1825670034
Short name T305
Test name
Test status
Simulation time 27852464 ps
CPU time 0.71 seconds
Started Jul 28 05:13:58 PM PDT 24
Finished Jul 28 05:13:58 PM PDT 24
Peak memory 195072 kb
Host smart-9197e4b5-3642-4e31-9b2f-8afa580dcc33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825670034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1825670034
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.4080577937
Short name T197
Test name
Test status
Simulation time 123950732 ps
CPU time 1.02 seconds
Started Jul 28 05:13:59 PM PDT 24
Finished Jul 28 05:14:00 PM PDT 24
Peak memory 196456 kb
Host smart-c6468250-284b-40ee-9ab3-088ad8c8c1d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080577937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.4080577937
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1881118279
Short name T697
Test name
Test status
Simulation time 359150894 ps
CPU time 3.48 seconds
Started Jul 28 05:13:52 PM PDT 24
Finished Jul 28 05:13:56 PM PDT 24
Peak memory 196952 kb
Host smart-0188eb86-e486-407e-af72-05a9e05c50f0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881118279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1881118279
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3314629606
Short name T570
Test name
Test status
Simulation time 188535535 ps
CPU time 2.1 seconds
Started Jul 28 05:13:49 PM PDT 24
Finished Jul 28 05:13:52 PM PDT 24
Peak memory 197504 kb
Host smart-a75ee968-7ed6-4653-8a31-07434bee0f3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314629606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3314629606
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.542292129
Short name T184
Test name
Test status
Simulation time 57182590 ps
CPU time 1.18 seconds
Started Jul 28 05:13:54 PM PDT 24
Finished Jul 28 05:13:56 PM PDT 24
Peak memory 197544 kb
Host smart-aa98f832-6208-4d33-8cb2-9426c2ae0252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542292129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.542292129
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3579720000
Short name T306
Test name
Test status
Simulation time 216108531 ps
CPU time 0.7 seconds
Started Jul 28 05:13:58 PM PDT 24
Finished Jul 28 05:13:59 PM PDT 24
Peak memory 194752 kb
Host smart-c1dcc835-abf7-4178-b8c1-67aabae236d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579720000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.3579720000
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.231774913
Short name T193
Test name
Test status
Simulation time 32695740 ps
CPU time 1.56 seconds
Started Jul 28 05:14:12 PM PDT 24
Finished Jul 28 05:14:14 PM PDT 24
Peak memory 198680 kb
Host smart-0eea2051-0d47-4090-a392-1dd151653da2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231774913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ran
dom_long_reg_writes_reg_reads.231774913
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2770149506
Short name T101
Test name
Test status
Simulation time 585283575 ps
CPU time 0.94 seconds
Started Jul 28 05:14:01 PM PDT 24
Finished Jul 28 05:14:02 PM PDT 24
Peak memory 195864 kb
Host smart-a5f0195b-c732-428f-bc29-b0a5cf537cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770149506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2770149506
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3683350302
Short name T274
Test name
Test status
Simulation time 24851125 ps
CPU time 0.8 seconds
Started Jul 28 05:14:03 PM PDT 24
Finished Jul 28 05:14:04 PM PDT 24
Peak memory 196476 kb
Host smart-21df8630-cf08-4852-bb05-c3248e1caf27
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683350302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3683350302
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2718601360
Short name T653
Test name
Test status
Simulation time 13787207864 ps
CPU time 96.21 seconds
Started Jul 28 05:13:58 PM PDT 24
Finished Jul 28 05:15:35 PM PDT 24
Peak memory 198536 kb
Host smart-118b67d7-e17e-4d14-aff0-3becec8117b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718601360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2718601360
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.1613353498
Short name T47
Test name
Test status
Simulation time 326025035288 ps
CPU time 2119.59 seconds
Started Jul 28 05:13:59 PM PDT 24
Finished Jul 28 05:49:19 PM PDT 24
Peak memory 198696 kb
Host smart-cf4c173c-63cf-4c7d-9379-b1d11c0e3382
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1613353498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.1613353498
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.637089846
Short name T690
Test name
Test status
Simulation time 40309667 ps
CPU time 0.62 seconds
Started Jul 28 05:13:59 PM PDT 24
Finished Jul 28 05:14:00 PM PDT 24
Peak memory 194468 kb
Host smart-1ed6f819-2b9f-484b-9d01-27766ac201b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637089846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.637089846
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1028692207
Short name T398
Test name
Test status
Simulation time 58120683 ps
CPU time 0.63 seconds
Started Jul 28 05:13:49 PM PDT 24
Finished Jul 28 05:13:50 PM PDT 24
Peak memory 194552 kb
Host smart-f736dfdd-f082-4bcb-a3da-6165541f702e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028692207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1028692207
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2009733802
Short name T209
Test name
Test status
Simulation time 334429006 ps
CPU time 10.04 seconds
Started Jul 28 05:13:59 PM PDT 24
Finished Jul 28 05:14:09 PM PDT 24
Peak memory 198508 kb
Host smart-fcde1978-bb71-430e-ae3d-9c1e55aa1f57
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009733802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2009733802
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.2929137125
Short name T561
Test name
Test status
Simulation time 27986866 ps
CPU time 0.73 seconds
Started Jul 28 05:14:05 PM PDT 24
Finished Jul 28 05:14:06 PM PDT 24
Peak memory 195284 kb
Host smart-284755fe-be45-47bf-a03b-dc20fa04fb09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929137125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.2929137125
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2377360730
Short name T200
Test name
Test status
Simulation time 521540659 ps
CPU time 1.32 seconds
Started Jul 28 05:14:10 PM PDT 24
Finished Jul 28 05:14:16 PM PDT 24
Peak memory 196324 kb
Host smart-697b9f36-2b0c-4386-a87b-e0b100a4c6ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377360730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2377360730
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1602394970
Short name T438
Test name
Test status
Simulation time 25216458 ps
CPU time 1.04 seconds
Started Jul 28 05:14:13 PM PDT 24
Finished Jul 28 05:14:14 PM PDT 24
Peak memory 196408 kb
Host smart-01ba25a2-df87-4c6c-b86d-a0c7d5be0684
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602394970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1602394970
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2792136558
Short name T373
Test name
Test status
Simulation time 525831472 ps
CPU time 3.66 seconds
Started Jul 28 05:13:59 PM PDT 24
Finished Jul 28 05:14:03 PM PDT 24
Peak memory 197024 kb
Host smart-f89107a1-0bef-46db-900e-c1b531ec0540
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792136558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2792136558
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2464259934
Short name T520
Test name
Test status
Simulation time 27615879 ps
CPU time 0.92 seconds
Started Jul 28 05:13:59 PM PDT 24
Finished Jul 28 05:14:00 PM PDT 24
Peak memory 196248 kb
Host smart-f750af4a-540d-452d-be62-1c10ba57faf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464259934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2464259934
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3382216354
Short name T267
Test name
Test status
Simulation time 294999909 ps
CPU time 0.82 seconds
Started Jul 28 05:13:52 PM PDT 24
Finished Jul 28 05:13:52 PM PDT 24
Peak memory 196012 kb
Host smart-a482bbf4-0357-4a9d-aced-c91d81208242
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382216354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3382216354
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.894925714
Short name T695
Test name
Test status
Simulation time 647421070 ps
CPU time 4.28 seconds
Started Jul 28 05:13:54 PM PDT 24
Finished Jul 28 05:13:59 PM PDT 24
Peak memory 198420 kb
Host smart-b2d5e2d8-4385-41d7-945e-8832c5128385
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894925714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.894925714
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.2149585345
Short name T699
Test name
Test status
Simulation time 182212928 ps
CPU time 1.08 seconds
Started Jul 28 05:14:02 PM PDT 24
Finished Jul 28 05:14:03 PM PDT 24
Peak memory 196088 kb
Host smart-93d45e5c-68ce-4443-bdc2-411c5703182d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149585345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2149585345
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3243277415
Short name T363
Test name
Test status
Simulation time 42706584 ps
CPU time 0.89 seconds
Started Jul 28 05:14:06 PM PDT 24
Finished Jul 28 05:14:07 PM PDT 24
Peak memory 196516 kb
Host smart-615697fd-d980-4bef-a534-0b3983f54667
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243277415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3243277415
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3236588594
Short name T7
Test name
Test status
Simulation time 2432299822 ps
CPU time 27.07 seconds
Started Jul 28 05:14:04 PM PDT 24
Finished Jul 28 05:14:31 PM PDT 24
Peak memory 198552 kb
Host smart-7faa2a3c-303d-4640-b7e3-325aeb036094
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236588594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3236588594
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.28669473
Short name T264
Test name
Test status
Simulation time 21055763 ps
CPU time 0.57 seconds
Started Jul 28 05:14:05 PM PDT 24
Finished Jul 28 05:14:06 PM PDT 24
Peak memory 194436 kb
Host smart-0d5bb86e-5fb3-4d4b-803c-82eddb967300
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28669473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.28669473
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2435677859
Short name T565
Test name
Test status
Simulation time 24396793 ps
CPU time 0.68 seconds
Started Jul 28 05:13:59 PM PDT 24
Finished Jul 28 05:13:59 PM PDT 24
Peak memory 196460 kb
Host smart-decd0dab-7ce3-4e74-90e0-807079ca359b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435677859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2435677859
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.667886243
Short name T125
Test name
Test status
Simulation time 1049732964 ps
CPU time 8.83 seconds
Started Jul 28 05:14:06 PM PDT 24
Finished Jul 28 05:14:15 PM PDT 24
Peak memory 196008 kb
Host smart-e40249d1-9996-45ed-8433-86131377144c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667886243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.667886243
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.290152232
Short name T625
Test name
Test status
Simulation time 132349336 ps
CPU time 0.69 seconds
Started Jul 28 05:13:54 PM PDT 24
Finished Jul 28 05:13:55 PM PDT 24
Peak memory 195136 kb
Host smart-565a63db-2554-4d50-9368-fff0fe29e319
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290152232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.290152232
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1263049394
Short name T145
Test name
Test status
Simulation time 25674737 ps
CPU time 0.7 seconds
Started Jul 28 05:14:04 PM PDT 24
Finished Jul 28 05:14:04 PM PDT 24
Peak memory 194760 kb
Host smart-1b01ded7-ed32-4858-87c8-116baa712907
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263049394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1263049394
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1891534556
Short name T214
Test name
Test status
Simulation time 686306364 ps
CPU time 3.62 seconds
Started Jul 28 05:14:02 PM PDT 24
Finished Jul 28 05:14:06 PM PDT 24
Peak memory 198612 kb
Host smart-489815f6-5df1-4703-9250-e7ecdd7f8c8b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891534556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1891534556
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2569703819
Short name T664
Test name
Test status
Simulation time 478732412 ps
CPU time 2.33 seconds
Started Jul 28 05:14:05 PM PDT 24
Finished Jul 28 05:14:07 PM PDT 24
Peak memory 197480 kb
Host smart-fcbff972-e89d-4065-9600-6f131f595eb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569703819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2569703819
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3662990085
Short name T502
Test name
Test status
Simulation time 18890662 ps
CPU time 0.75 seconds
Started Jul 28 05:14:10 PM PDT 24
Finished Jul 28 05:14:11 PM PDT 24
Peak memory 196024 kb
Host smart-d6c34ed1-0bfe-4109-9d75-6dd04a043eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662990085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3662990085
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3159131621
Short name T347
Test name
Test status
Simulation time 237433660 ps
CPU time 1.35 seconds
Started Jul 28 05:13:58 PM PDT 24
Finished Jul 28 05:14:00 PM PDT 24
Peak memory 196304 kb
Host smart-99ef3bab-fe0c-4d06-919a-f3341486d21f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159131621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3159131621
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2753991051
Short name T604
Test name
Test status
Simulation time 81444969 ps
CPU time 3.37 seconds
Started Jul 28 05:14:02 PM PDT 24
Finished Jul 28 05:14:06 PM PDT 24
Peak memory 198412 kb
Host smart-d568dfc7-dd3d-4879-9f7d-412210786408
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753991051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2753991051
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2119123712
Short name T475
Test name
Test status
Simulation time 54263729 ps
CPU time 1.17 seconds
Started Jul 28 05:14:02 PM PDT 24
Finished Jul 28 05:14:04 PM PDT 24
Peak memory 196016 kb
Host smart-1bf55302-5099-42c5-9e3d-88e5ddc0b272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119123712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2119123712
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.4207144287
Short name T655
Test name
Test status
Simulation time 23138688 ps
CPU time 0.82 seconds
Started Jul 28 05:14:06 PM PDT 24
Finished Jul 28 05:14:07 PM PDT 24
Peak memory 195596 kb
Host smart-f3615e38-95e3-44e1-9271-ba80ee79b6e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207144287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.4207144287
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.581558250
Short name T411
Test name
Test status
Simulation time 2154116891 ps
CPU time 30.31 seconds
Started Jul 28 05:14:03 PM PDT 24
Finished Jul 28 05:14:33 PM PDT 24
Peak memory 198592 kb
Host smart-c33c0382-5db0-4db4-b887-0e3bd21e6a06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581558250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.581558250
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1102350493
Short name T36
Test name
Test status
Simulation time 32756905 ps
CPU time 0.58 seconds
Started Jul 28 05:14:02 PM PDT 24
Finished Jul 28 05:14:02 PM PDT 24
Peak memory 195096 kb
Host smart-e2c74dd9-c56a-4a0d-b782-b82bbcee14f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102350493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1102350493
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1310839807
Short name T229
Test name
Test status
Simulation time 497700304 ps
CPU time 0.86 seconds
Started Jul 28 05:13:57 PM PDT 24
Finished Jul 28 05:13:58 PM PDT 24
Peak memory 196220 kb
Host smart-ee6fe572-9b54-4f9d-9ee1-e04a36f55ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310839807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1310839807
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2565802918
Short name T138
Test name
Test status
Simulation time 3749956854 ps
CPU time 26.13 seconds
Started Jul 28 05:14:02 PM PDT 24
Finished Jul 28 05:14:29 PM PDT 24
Peak memory 197244 kb
Host smart-1caa86a0-b593-4c1f-83d0-faeb45e82593
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565802918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2565802918
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1912717004
Short name T297
Test name
Test status
Simulation time 64149606 ps
CPU time 1.05 seconds
Started Jul 28 05:14:09 PM PDT 24
Finished Jul 28 05:14:10 PM PDT 24
Peak memory 198536 kb
Host smart-ac75bf60-f934-4938-944f-6730acbe62c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912717004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1912717004
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.248587857
Short name T470
Test name
Test status
Simulation time 204100629 ps
CPU time 1.31 seconds
Started Jul 28 05:14:03 PM PDT 24
Finished Jul 28 05:14:04 PM PDT 24
Peak memory 197372 kb
Host smart-b2d2fb49-a7c3-4da9-8dbf-b533f825f844
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248587857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.248587857
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.51734107
Short name T369
Test name
Test status
Simulation time 168715338 ps
CPU time 3.52 seconds
Started Jul 28 05:13:59 PM PDT 24
Finished Jul 28 05:14:03 PM PDT 24
Peak memory 197640 kb
Host smart-b12b54e9-a561-477b-8676-20e43b9d9e8b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51734107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.gpio_intr_with_filter_rand_intr_event.51734107
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.979295973
Short name T242
Test name
Test status
Simulation time 82221752 ps
CPU time 2.32 seconds
Started Jul 28 05:14:07 PM PDT 24
Finished Jul 28 05:14:09 PM PDT 24
Peak memory 198592 kb
Host smart-d78f8372-a981-4685-89a4-c123c09bd5ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979295973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
979295973
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.111304642
Short name T318
Test name
Test status
Simulation time 209355526 ps
CPU time 0.97 seconds
Started Jul 28 05:14:09 PM PDT 24
Finished Jul 28 05:14:10 PM PDT 24
Peak memory 196460 kb
Host smart-f1bb2637-f5de-4457-8da7-f4e395d7b166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111304642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.111304642
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3022411964
Short name T639
Test name
Test status
Simulation time 60464368 ps
CPU time 1.3 seconds
Started Jul 28 05:14:14 PM PDT 24
Finished Jul 28 05:14:15 PM PDT 24
Peak memory 198740 kb
Host smart-193b3889-36e3-4a3d-a2b1-644d7a812663
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022411964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3022411964
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3252321912
Short name T346
Test name
Test status
Simulation time 308074189 ps
CPU time 3.81 seconds
Started Jul 28 05:14:00 PM PDT 24
Finished Jul 28 05:14:04 PM PDT 24
Peak memory 198448 kb
Host smart-a6a6b172-2bd1-4b40-9c3c-7c9de896e9f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252321912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3252321912
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2042856541
Short name T174
Test name
Test status
Simulation time 355056596 ps
CPU time 1.53 seconds
Started Jul 28 05:14:00 PM PDT 24
Finished Jul 28 05:14:02 PM PDT 24
Peak memory 197188 kb
Host smart-1279f3df-a889-4e41-b006-4f7786d89ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042856541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2042856541
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1996204941
Short name T463
Test name
Test status
Simulation time 72485973 ps
CPU time 1.37 seconds
Started Jul 28 05:14:04 PM PDT 24
Finished Jul 28 05:14:05 PM PDT 24
Peak memory 195968 kb
Host smart-aed5e06e-b4ec-4067-9d75-2946fac80c4b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996204941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1996204941
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1054830621
Short name T20
Test name
Test status
Simulation time 10375869851 ps
CPU time 108.52 seconds
Started Jul 28 05:14:13 PM PDT 24
Finished Jul 28 05:16:01 PM PDT 24
Peak memory 198604 kb
Host smart-2afd458d-167f-4bab-bf3e-023fe20d2da7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054830621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1054830621
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.4094075725
Short name T50
Test name
Test status
Simulation time 78453208376 ps
CPU time 616 seconds
Started Jul 28 05:14:01 PM PDT 24
Finished Jul 28 05:24:17 PM PDT 24
Peak memory 198832 kb
Host smart-ac4b1ce5-bbf1-4a84-8e50-af89c052bb9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4094075725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.4094075725
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.721406024
Short name T609
Test name
Test status
Simulation time 39286011 ps
CPU time 0.58 seconds
Started Jul 28 05:14:07 PM PDT 24
Finished Jul 28 05:14:07 PM PDT 24
Peak memory 195104 kb
Host smart-89747b2b-0eac-4ca0-8a76-d21e4888542e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721406024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.721406024
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3476445587
Short name T282
Test name
Test status
Simulation time 93250767 ps
CPU time 0.7 seconds
Started Jul 28 05:13:59 PM PDT 24
Finished Jul 28 05:14:00 PM PDT 24
Peak memory 196428 kb
Host smart-86a25007-1a25-4b36-b156-4e84ad1a1b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476445587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3476445587
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1590940894
Short name T336
Test name
Test status
Simulation time 2844270433 ps
CPU time 20.55 seconds
Started Jul 28 05:14:07 PM PDT 24
Finished Jul 28 05:14:28 PM PDT 24
Peak memory 197368 kb
Host smart-dd7ba81e-aa78-4c9d-8a48-d015af7dc466
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590940894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1590940894
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1605042567
Short name T401
Test name
Test status
Simulation time 182155648 ps
CPU time 0.93 seconds
Started Jul 28 05:14:14 PM PDT 24
Finished Jul 28 05:14:16 PM PDT 24
Peak memory 198368 kb
Host smart-cc5ce211-551a-4694-929a-e2765d47a025
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605042567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1605042567
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.4194122392
Short name T247
Test name
Test status
Simulation time 39155454 ps
CPU time 0.68 seconds
Started Jul 28 05:14:11 PM PDT 24
Finished Jul 28 05:14:11 PM PDT 24
Peak memory 195824 kb
Host smart-57ad2e63-808f-4cd7-a6f4-f60d321dcf04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194122392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.4194122392
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.1810821783
Short name T223
Test name
Test status
Simulation time 60333457 ps
CPU time 2.36 seconds
Started Jul 28 05:14:11 PM PDT 24
Finished Jul 28 05:14:14 PM PDT 24
Peak memory 198576 kb
Host smart-c60a267b-5911-49b9-9c96-a2b28614aa5f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810821783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.1810821783
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.457580064
Short name T196
Test name
Test status
Simulation time 145808946 ps
CPU time 2.98 seconds
Started Jul 28 05:14:06 PM PDT 24
Finished Jul 28 05:14:09 PM PDT 24
Peak memory 196288 kb
Host smart-6141d326-118b-4fd2-a1d9-ba8b76b286cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457580064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger.
457580064
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3689895466
Short name T383
Test name
Test status
Simulation time 95256574 ps
CPU time 1 seconds
Started Jul 28 05:14:05 PM PDT 24
Finished Jul 28 05:14:06 PM PDT 24
Peak memory 196580 kb
Host smart-c3f9df81-dbe2-428b-ad41-850c3b03f8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689895466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3689895466
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3560828051
Short name T618
Test name
Test status
Simulation time 264703980 ps
CPU time 1.15 seconds
Started Jul 28 05:13:59 PM PDT 24
Finished Jul 28 05:14:01 PM PDT 24
Peak memory 197432 kb
Host smart-89fc4aa6-6988-402e-a086-50db724c8a49
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560828051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.3560828051
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.380503575
Short name T505
Test name
Test status
Simulation time 86295838 ps
CPU time 3.96 seconds
Started Jul 28 05:14:12 PM PDT 24
Finished Jul 28 05:14:16 PM PDT 24
Peak memory 198464 kb
Host smart-debe6c95-3421-4a16-96d8-f4794443603f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380503575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ran
dom_long_reg_writes_reg_reads.380503575
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.1145274273
Short name T660
Test name
Test status
Simulation time 109023379 ps
CPU time 0.88 seconds
Started Jul 28 05:14:01 PM PDT 24
Finished Jul 28 05:14:02 PM PDT 24
Peak memory 196720 kb
Host smart-51fa08a4-0e7d-4974-8130-8323d3530605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145274273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1145274273
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3296441025
Short name T303
Test name
Test status
Simulation time 414729587 ps
CPU time 1.08 seconds
Started Jul 28 05:14:04 PM PDT 24
Finished Jul 28 05:14:05 PM PDT 24
Peak memory 195488 kb
Host smart-271345bc-4212-42be-9147-ba4282edb445
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296441025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3296441025
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.792208616
Short name T189
Test name
Test status
Simulation time 24286995700 ps
CPU time 151.62 seconds
Started Jul 28 05:14:07 PM PDT 24
Finished Jul 28 05:16:39 PM PDT 24
Peak memory 198588 kb
Host smart-1936e731-4f83-41b1-b0d9-528b3a543bfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792208616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.792208616
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3513372461
Short name T476
Test name
Test status
Simulation time 12885050 ps
CPU time 0.57 seconds
Started Jul 28 05:14:07 PM PDT 24
Finished Jul 28 05:14:08 PM PDT 24
Peak memory 195128 kb
Host smart-38779b27-a53c-4c05-89a7-feef13ce6f96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513372461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3513372461
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.2144778763
Short name T608
Test name
Test status
Simulation time 351667933 ps
CPU time 0.83 seconds
Started Jul 28 05:14:02 PM PDT 24
Finished Jul 28 05:14:03 PM PDT 24
Peak memory 197556 kb
Host smart-c452f254-453a-41a1-9eed-6ab5ae780889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144778763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.2144778763
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.4162332315
Short name T182
Test name
Test status
Simulation time 750029916 ps
CPU time 12.07 seconds
Started Jul 28 05:14:03 PM PDT 24
Finished Jul 28 05:14:15 PM PDT 24
Peak memory 196732 kb
Host smart-36345671-8725-4c56-84e7-cd6e74a61a6c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162332315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.4162332315
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.28075106
Short name T687
Test name
Test status
Simulation time 93454497 ps
CPU time 1.14 seconds
Started Jul 28 05:14:03 PM PDT 24
Finished Jul 28 05:14:05 PM PDT 24
Peak memory 198436 kb
Host smart-3e9e2e7f-cfeb-41f5-a1f9-e756fbb45169
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28075106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.28075106
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2674564175
Short name T296
Test name
Test status
Simulation time 107422732 ps
CPU time 0.7 seconds
Started Jul 28 05:14:03 PM PDT 24
Finished Jul 28 05:14:04 PM PDT 24
Peak memory 195844 kb
Host smart-e0ca8895-3985-4dee-916a-f560f7137b75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674564175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2674564175
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.237737329
Short name T320
Test name
Test status
Simulation time 94589966 ps
CPU time 1.98 seconds
Started Jul 28 05:14:13 PM PDT 24
Finished Jul 28 05:14:15 PM PDT 24
Peak memory 198564 kb
Host smart-98361cad-14b1-4333-8e0e-1c9d31a11b37
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237737329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.237737329
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.4224408807
Short name T205
Test name
Test status
Simulation time 325209532 ps
CPU time 1.94 seconds
Started Jul 28 05:14:07 PM PDT 24
Finished Jul 28 05:14:09 PM PDT 24
Peak memory 196320 kb
Host smart-55cd6c44-6f31-4f94-af32-8be8e04095cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224408807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.4224408807
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.191994286
Short name T387
Test name
Test status
Simulation time 24252358 ps
CPU time 0.84 seconds
Started Jul 28 05:14:07 PM PDT 24
Finished Jul 28 05:14:08 PM PDT 24
Peak memory 197204 kb
Host smart-355ff437-f254-4505-8575-49c08f15d3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191994286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.191994286
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.287386058
Short name T466
Test name
Test status
Simulation time 33123830 ps
CPU time 0.85 seconds
Started Jul 28 05:14:09 PM PDT 24
Finished Jul 28 05:14:09 PM PDT 24
Peak memory 197064 kb
Host smart-5c5fb5ae-57c3-4681-aa6c-5218c862644f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287386058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.287386058
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2976520308
Short name T201
Test name
Test status
Simulation time 48284275 ps
CPU time 1.1 seconds
Started Jul 28 05:14:08 PM PDT 24
Finished Jul 28 05:14:09 PM PDT 24
Peak memory 197096 kb
Host smart-78240588-457a-4956-b1d7-d22215b54381
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976520308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2976520308
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2072887193
Short name T338
Test name
Test status
Simulation time 43400638 ps
CPU time 1.22 seconds
Started Jul 28 05:14:05 PM PDT 24
Finished Jul 28 05:14:06 PM PDT 24
Peak memory 196504 kb
Host smart-fb07178f-e521-49e2-901c-0f1821e77ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072887193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2072887193
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.240078806
Short name T498
Test name
Test status
Simulation time 40283444 ps
CPU time 1.23 seconds
Started Jul 28 05:14:07 PM PDT 24
Finished Jul 28 05:14:09 PM PDT 24
Peak memory 196060 kb
Host smart-b352ccc5-ce04-4fc1-ad2e-8e056ea54e30
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240078806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.240078806
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.2284760599
Short name T353
Test name
Test status
Simulation time 28209192496 ps
CPU time 96.34 seconds
Started Jul 28 05:13:58 PM PDT 24
Finished Jul 28 05:15:35 PM PDT 24
Peak memory 198564 kb
Host smart-b3110078-64d0-49af-b6f3-ea3b8e1a195a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284760599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.2284760599
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.598002345
Short name T715
Test name
Test status
Simulation time 33324669 ps
CPU time 0.56 seconds
Started Jul 28 05:13:34 PM PDT 24
Finished Jul 28 05:13:35 PM PDT 24
Peak memory 194384 kb
Host smart-cb63e480-3a88-469b-9a40-bd0883e8f538
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598002345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.598002345
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3628520649
Short name T375
Test name
Test status
Simulation time 66094591 ps
CPU time 0.68 seconds
Started Jul 28 05:13:48 PM PDT 24
Finished Jul 28 05:13:49 PM PDT 24
Peak memory 195088 kb
Host smart-6386f18c-c804-4285-822f-f3cc09e86987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628520649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3628520649
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2327099271
Short name T251
Test name
Test status
Simulation time 101438275 ps
CPU time 4.78 seconds
Started Jul 28 05:13:36 PM PDT 24
Finished Jul 28 05:13:41 PM PDT 24
Peak memory 196924 kb
Host smart-777691f4-7f43-4dca-9a1c-4f20bb63690a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327099271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2327099271
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.4162486054
Short name T186
Test name
Test status
Simulation time 69421823 ps
CPU time 0.69 seconds
Started Jul 28 05:13:32 PM PDT 24
Finished Jul 28 05:13:33 PM PDT 24
Peak memory 196216 kb
Host smart-5b1eed93-e846-4719-887c-4e73edd4c038
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162486054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.4162486054
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.3363640506
Short name T152
Test name
Test status
Simulation time 731712648 ps
CPU time 1.02 seconds
Started Jul 28 05:13:29 PM PDT 24
Finished Jul 28 05:13:31 PM PDT 24
Peak memory 196604 kb
Host smart-f4ba39f9-f0ac-4ef4-bde0-f51bfc995905
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363640506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.3363640506
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3841316841
Short name T444
Test name
Test status
Simulation time 94862869 ps
CPU time 3.53 seconds
Started Jul 28 05:13:28 PM PDT 24
Finished Jul 28 05:13:31 PM PDT 24
Peak memory 198676 kb
Host smart-f6f4f94d-e71c-409f-859f-483dc9d94cef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841316841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3841316841
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.1949066808
Short name T562
Test name
Test status
Simulation time 1883922378 ps
CPU time 2.71 seconds
Started Jul 28 05:13:29 PM PDT 24
Finished Jul 28 05:13:33 PM PDT 24
Peak memory 197512 kb
Host smart-048eb360-45c3-4794-be89-06bc2c4dc86a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949066808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
1949066808
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2088230127
Short name T327
Test name
Test status
Simulation time 56122116 ps
CPU time 1.09 seconds
Started Jul 28 05:13:33 PM PDT 24
Finished Jul 28 05:13:34 PM PDT 24
Peak memory 196960 kb
Host smart-9d93a075-a91f-45ac-9825-44cd2320e7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088230127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2088230127
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.117337943
Short name T119
Test name
Test status
Simulation time 578954161 ps
CPU time 1.19 seconds
Started Jul 28 05:13:37 PM PDT 24
Finished Jul 28 05:13:38 PM PDT 24
Peak memory 197472 kb
Host smart-4080c2de-2c9e-4873-88b0-ae4e03c24888
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117337943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_
pulldown.117337943
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.874488614
Short name T548
Test name
Test status
Simulation time 123074734 ps
CPU time 5.27 seconds
Started Jul 28 05:13:34 PM PDT 24
Finished Jul 28 05:13:39 PM PDT 24
Peak memory 198440 kb
Host smart-790a4fc5-1acc-4da9-a9ac-c16a10643a3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874488614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.874488614
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_smoke.2028707513
Short name T611
Test name
Test status
Simulation time 208129027 ps
CPU time 1.05 seconds
Started Jul 28 05:13:23 PM PDT 24
Finished Jul 28 05:13:24 PM PDT 24
Peak memory 196124 kb
Host smart-03ff54d7-c988-4558-8f3e-d25c1da24e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028707513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2028707513
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2588848274
Short name T248
Test name
Test status
Simulation time 94743528 ps
CPU time 1.47 seconds
Started Jul 28 05:13:32 PM PDT 24
Finished Jul 28 05:13:34 PM PDT 24
Peak memory 197304 kb
Host smart-50a96834-e46d-4795-b339-205f4a7ac72f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588848274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2588848274
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3349323041
Short name T272
Test name
Test status
Simulation time 186547174720 ps
CPU time 136.76 seconds
Started Jul 28 05:13:28 PM PDT 24
Finished Jul 28 05:15:45 PM PDT 24
Peak memory 198564 kb
Host smart-6738b2dc-a617-4ef8-83c6-e35b63df94c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349323041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3349323041
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.199074029
Short name T49
Test name
Test status
Simulation time 110696239043 ps
CPU time 729.9 seconds
Started Jul 28 05:13:33 PM PDT 24
Finished Jul 28 05:25:43 PM PDT 24
Peak memory 198684 kb
Host smart-a841deb6-669f-4b80-8e63-eb98403c7d3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=199074029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.199074029
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2742601991
Short name T451
Test name
Test status
Simulation time 20022259 ps
CPU time 0.57 seconds
Started Jul 28 05:14:09 PM PDT 24
Finished Jul 28 05:14:10 PM PDT 24
Peak memory 194360 kb
Host smart-3a66473c-d2fa-46e6-ae58-03fa606a98d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742601991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2742601991
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.3736277482
Short name T290
Test name
Test status
Simulation time 110694075 ps
CPU time 0.78 seconds
Started Jul 28 05:14:05 PM PDT 24
Finished Jul 28 05:14:06 PM PDT 24
Peak memory 195736 kb
Host smart-34de27f9-ee83-4ef3-8938-825ba5e678ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736277482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.3736277482
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.3965999378
Short name T662
Test name
Test status
Simulation time 766213955 ps
CPU time 20.32 seconds
Started Jul 28 05:14:05 PM PDT 24
Finished Jul 28 05:14:25 PM PDT 24
Peak memory 197260 kb
Host smart-3997b9a1-2690-42fc-8853-499690444fa0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965999378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.3965999378
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.4267945668
Short name T566
Test name
Test status
Simulation time 139480877 ps
CPU time 0.83 seconds
Started Jul 28 05:14:10 PM PDT 24
Finished Jul 28 05:14:11 PM PDT 24
Peak memory 197176 kb
Host smart-b6485bc2-5faa-4478-bf97-d677ff81a189
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267945668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.4267945668
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.3155089500
Short name T537
Test name
Test status
Simulation time 51069049 ps
CPU time 0.97 seconds
Started Jul 28 05:14:17 PM PDT 24
Finished Jul 28 05:14:18 PM PDT 24
Peak memory 197052 kb
Host smart-1114c8b8-3f16-44a3-a27f-9f923222a06d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155089500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.3155089500
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1387802906
Short name T528
Test name
Test status
Simulation time 72208678 ps
CPU time 1.39 seconds
Started Jul 28 05:14:13 PM PDT 24
Finished Jul 28 05:14:14 PM PDT 24
Peak memory 198580 kb
Host smart-20b9f2cc-c22f-4ac0-9409-1dd1373d3154
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387802906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1387802906
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.988364362
Short name T691
Test name
Test status
Simulation time 47924853 ps
CPU time 1.52 seconds
Started Jul 28 05:14:06 PM PDT 24
Finished Jul 28 05:14:07 PM PDT 24
Peak memory 196276 kb
Host smart-8ee7b13e-4992-4c36-9957-3cca8bb287e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988364362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger.
988364362
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.382698215
Short name T619
Test name
Test status
Simulation time 59274211 ps
CPU time 0.81 seconds
Started Jul 28 05:14:05 PM PDT 24
Finished Jul 28 05:14:06 PM PDT 24
Peak memory 197012 kb
Host smart-95341567-f5d8-4134-9ec9-57c03a1d6947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382698215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.382698215
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3039800794
Short name T577
Test name
Test status
Simulation time 26972009 ps
CPU time 0.89 seconds
Started Jul 28 05:14:01 PM PDT 24
Finished Jul 28 05:14:02 PM PDT 24
Peak memory 197016 kb
Host smart-7f2f75c2-c350-4360-94c7-dd26ef42d8e1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039800794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3039800794
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1716911545
Short name T493
Test name
Test status
Simulation time 232977237 ps
CPU time 4.87 seconds
Started Jul 28 05:14:09 PM PDT 24
Finished Jul 28 05:14:14 PM PDT 24
Peak memory 198392 kb
Host smart-21bfe65f-73d2-47e9-866b-0d355df3a423
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716911545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1716911545
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.4129718103
Short name T111
Test name
Test status
Simulation time 250103176 ps
CPU time 1.36 seconds
Started Jul 28 05:14:00 PM PDT 24
Finished Jul 28 05:14:02 PM PDT 24
Peak memory 198476 kb
Host smart-42a1adc1-ddcf-444c-b326-9edddf4d8137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129718103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.4129718103
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3945215749
Short name T559
Test name
Test status
Simulation time 125694045 ps
CPU time 1.02 seconds
Started Jul 28 05:14:11 PM PDT 24
Finished Jul 28 05:14:13 PM PDT 24
Peak memory 196272 kb
Host smart-ac9ffe3f-4037-4cb5-a96f-a33378f11429
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945215749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3945215749
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.520757829
Short name T495
Test name
Test status
Simulation time 36679215424 ps
CPU time 216.61 seconds
Started Jul 28 05:14:08 PM PDT 24
Finished Jul 28 05:17:45 PM PDT 24
Peak memory 198688 kb
Host smart-e4dd2dbc-7db1-42ec-9cc7-93b95c2781f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520757829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.g
pio_stress_all.520757829
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2504119476
Short name T350
Test name
Test status
Simulation time 27241732 ps
CPU time 0.58 seconds
Started Jul 28 05:14:15 PM PDT 24
Finished Jul 28 05:14:16 PM PDT 24
Peak memory 194392 kb
Host smart-4466948e-f4d5-4b4d-8b68-c51b166c71cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504119476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2504119476
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.358654071
Short name T636
Test name
Test status
Simulation time 42223874 ps
CPU time 0.89 seconds
Started Jul 28 05:14:05 PM PDT 24
Finished Jul 28 05:14:06 PM PDT 24
Peak memory 196500 kb
Host smart-f09095aa-bf59-4b4b-a906-1f6956625280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358654071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.358654071
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2091374306
Short name T486
Test name
Test status
Simulation time 1295333916 ps
CPU time 20.91 seconds
Started Jul 28 05:14:22 PM PDT 24
Finished Jul 28 05:14:43 PM PDT 24
Peak memory 197244 kb
Host smart-e0bab418-a225-459f-abdc-dfbd4f9d34ed
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091374306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2091374306
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.1221270929
Short name T390
Test name
Test status
Simulation time 73623945 ps
CPU time 0.96 seconds
Started Jul 28 05:14:15 PM PDT 24
Finished Jul 28 05:14:16 PM PDT 24
Peak memory 198260 kb
Host smart-efa37eb6-ce0b-4fad-9b8c-61c878242bab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221270929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.1221270929
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2286887012
Short name T558
Test name
Test status
Simulation time 85144548 ps
CPU time 1.23 seconds
Started Jul 28 05:14:05 PM PDT 24
Finished Jul 28 05:14:06 PM PDT 24
Peak memory 198588 kb
Host smart-62c53fec-aa76-4c72-8606-e6c4bc8af73b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286887012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2286887012
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1614641502
Short name T637
Test name
Test status
Simulation time 19770901 ps
CPU time 0.9 seconds
Started Jul 28 05:14:07 PM PDT 24
Finished Jul 28 05:14:08 PM PDT 24
Peak memory 196756 kb
Host smart-79618eda-6404-489e-83d6-716d2ecf8cee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614641502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1614641502
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.74539084
Short name T623
Test name
Test status
Simulation time 117821821 ps
CPU time 2.54 seconds
Started Jul 28 05:14:06 PM PDT 24
Finished Jul 28 05:14:08 PM PDT 24
Peak memory 197592 kb
Host smart-36ab14db-81f4-4950-91b7-ce880f2195bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74539084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.74539084
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2988319476
Short name T429
Test name
Test status
Simulation time 164730827 ps
CPU time 1.07 seconds
Started Jul 28 05:14:06 PM PDT 24
Finished Jul 28 05:14:08 PM PDT 24
Peak memory 196440 kb
Host smart-76e93a5d-97cf-46e0-808a-50a26effa373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988319476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2988319476
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3672577686
Short name T54
Test name
Test status
Simulation time 44062409 ps
CPU time 0.89 seconds
Started Jul 28 05:14:10 PM PDT 24
Finished Jul 28 05:14:11 PM PDT 24
Peak memory 197020 kb
Host smart-e86730a4-a797-40a4-a7cd-23edf08e6175
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672577686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3672577686
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2839198272
Short name T503
Test name
Test status
Simulation time 742845829 ps
CPU time 3.46 seconds
Started Jul 28 05:14:10 PM PDT 24
Finished Jul 28 05:14:14 PM PDT 24
Peak memory 198416 kb
Host smart-43332217-f597-49de-84cb-0aac8f111351
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839198272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2839198272
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2256924825
Short name T256
Test name
Test status
Simulation time 40856383 ps
CPU time 0.76 seconds
Started Jul 28 05:14:05 PM PDT 24
Finished Jul 28 05:14:06 PM PDT 24
Peak memory 195728 kb
Host smart-178dfcb5-7afa-44f2-892f-5b5d9f4de3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256924825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2256924825
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1985600164
Short name T99
Test name
Test status
Simulation time 46949664 ps
CPU time 1.11 seconds
Started Jul 28 05:14:10 PM PDT 24
Finished Jul 28 05:14:11 PM PDT 24
Peak memory 196188 kb
Host smart-424f8f48-51bc-4dd4-b5d4-a74436617d16
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985600164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1985600164
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.3657712855
Short name T385
Test name
Test status
Simulation time 27687769169 ps
CPU time 181.03 seconds
Started Jul 28 05:14:07 PM PDT 24
Finished Jul 28 05:17:09 PM PDT 24
Peak memory 198572 kb
Host smart-48392318-300f-4652-929a-3e561accb32a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657712855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.3657712855
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.50076633
Short name T454
Test name
Test status
Simulation time 30925412 ps
CPU time 0.61 seconds
Started Jul 28 05:14:14 PM PDT 24
Finished Jul 28 05:14:14 PM PDT 24
Peak memory 195096 kb
Host smart-b86129d2-1c3c-4f88-b973-d927ad95ab15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50076633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.50076633
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1481761653
Short name T621
Test name
Test status
Simulation time 165485087 ps
CPU time 0.86 seconds
Started Jul 28 05:14:11 PM PDT 24
Finished Jul 28 05:14:12 PM PDT 24
Peak memory 196360 kb
Host smart-cc75eebf-9549-44c3-93d9-02161e15320e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481761653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1481761653
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2033509232
Short name T422
Test name
Test status
Simulation time 645759507 ps
CPU time 15.08 seconds
Started Jul 28 05:14:04 PM PDT 24
Finished Jul 28 05:14:19 PM PDT 24
Peak memory 198500 kb
Host smart-1e7e4672-eac4-452e-b169-7f0129766516
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033509232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2033509232
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3455077773
Short name T557
Test name
Test status
Simulation time 27974744 ps
CPU time 0.64 seconds
Started Jul 28 05:14:16 PM PDT 24
Finished Jul 28 05:14:17 PM PDT 24
Peak memory 194828 kb
Host smart-00845387-c486-4c6e-b930-536078676253
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455077773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3455077773
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.436149054
Short name T681
Test name
Test status
Simulation time 33625338 ps
CPU time 0.67 seconds
Started Jul 28 05:14:10 PM PDT 24
Finished Jul 28 05:14:10 PM PDT 24
Peak memory 195476 kb
Host smart-4e7cf878-d678-439a-b877-f0c2ee36e7f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436149054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.436149054
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.868412277
Short name T693
Test name
Test status
Simulation time 35083632 ps
CPU time 1.42 seconds
Started Jul 28 05:14:12 PM PDT 24
Finished Jul 28 05:14:14 PM PDT 24
Peak memory 196992 kb
Host smart-b30ba20a-4f86-42c7-b5b8-f42525fa129a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868412277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.868412277
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2051245358
Short name T442
Test name
Test status
Simulation time 93449741 ps
CPU time 2.01 seconds
Started Jul 28 05:14:07 PM PDT 24
Finished Jul 28 05:14:09 PM PDT 24
Peak memory 197592 kb
Host smart-248abd89-9f47-451c-9ea9-eb25de33c316
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051245358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2051245358
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.241760195
Short name T499
Test name
Test status
Simulation time 44820570 ps
CPU time 1 seconds
Started Jul 28 05:14:23 PM PDT 24
Finished Jul 28 05:14:24 PM PDT 24
Peak memory 196268 kb
Host smart-63682243-95fb-446a-b3d3-bc696d9f9bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241760195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.241760195
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.161842108
Short name T142
Test name
Test status
Simulation time 220932062 ps
CPU time 0.9 seconds
Started Jul 28 05:14:13 PM PDT 24
Finished Jul 28 05:14:14 PM PDT 24
Peak memory 196548 kb
Host smart-8d158257-7236-4802-bceb-8977baad9f14
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161842108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.161842108
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1898977717
Short name T508
Test name
Test status
Simulation time 143617996 ps
CPU time 3.37 seconds
Started Jul 28 05:14:11 PM PDT 24
Finished Jul 28 05:14:15 PM PDT 24
Peak memory 198444 kb
Host smart-5eec0b08-c2e1-47ab-951c-67f38c215530
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898977717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1898977717
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.4050510189
Short name T123
Test name
Test status
Simulation time 1395365682 ps
CPU time 1.29 seconds
Started Jul 28 05:14:11 PM PDT 24
Finished Jul 28 05:14:13 PM PDT 24
Peak memory 196900 kb
Host smart-e4bc460a-f29c-4697-ae21-5808101f597f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050510189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.4050510189
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2147259368
Short name T11
Test name
Test status
Simulation time 152673438 ps
CPU time 0.86 seconds
Started Jul 28 05:14:07 PM PDT 24
Finished Jul 28 05:14:08 PM PDT 24
Peak memory 197000 kb
Host smart-0dd0ed7d-3218-486a-95f7-5927b19ef1f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147259368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2147259368
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.3746490943
Short name T144
Test name
Test status
Simulation time 10700699450 ps
CPU time 143.29 seconds
Started Jul 28 05:14:17 PM PDT 24
Finished Jul 28 05:16:40 PM PDT 24
Peak memory 198568 kb
Host smart-1baf7008-a3d3-4102-ac48-297f98f6c3a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746490943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.3746490943
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.2502163555
Short name T484
Test name
Test status
Simulation time 194071275 ps
CPU time 0.6 seconds
Started Jul 28 05:14:15 PM PDT 24
Finished Jul 28 05:14:15 PM PDT 24
Peak memory 194352 kb
Host smart-c72efa60-749f-460a-a952-51ecdc348524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502163555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2502163555
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.403080782
Short name T535
Test name
Test status
Simulation time 34316825 ps
CPU time 0.62 seconds
Started Jul 28 05:14:09 PM PDT 24
Finished Jul 28 05:14:10 PM PDT 24
Peak memory 195216 kb
Host smart-d3d3a955-9a90-4e5e-9591-d502c271f5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403080782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.403080782
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.555251992
Short name T500
Test name
Test status
Simulation time 196952152 ps
CPU time 9.58 seconds
Started Jul 28 05:14:19 PM PDT 24
Finished Jul 28 05:14:29 PM PDT 24
Peak memory 197196 kb
Host smart-d33d75d7-7e19-439d-9b40-67f252e8defa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555251992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.555251992
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1648075254
Short name T8
Test name
Test status
Simulation time 93852549 ps
CPU time 0.64 seconds
Started Jul 28 05:14:05 PM PDT 24
Finished Jul 28 05:14:06 PM PDT 24
Peak memory 194948 kb
Host smart-af7da1de-60ca-4d5a-8edd-a3a19f15850f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648075254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1648075254
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.4199299047
Short name T102
Test name
Test status
Simulation time 68161645 ps
CPU time 0.84 seconds
Started Jul 28 05:14:14 PM PDT 24
Finished Jul 28 05:14:15 PM PDT 24
Peak memory 195876 kb
Host smart-0f800302-1b18-4d8c-ab0f-48c1643cc7e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199299047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.4199299047
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1254087588
Short name T217
Test name
Test status
Simulation time 148108647 ps
CPU time 2.74 seconds
Started Jul 28 05:14:27 PM PDT 24
Finished Jul 28 05:14:30 PM PDT 24
Peak memory 198492 kb
Host smart-36a2d923-f9cf-46dc-a691-85cbf837bf96
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254087588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1254087588
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2497914642
Short name T663
Test name
Test status
Simulation time 161878224 ps
CPU time 1.4 seconds
Started Jul 28 05:14:19 PM PDT 24
Finished Jul 28 05:14:20 PM PDT 24
Peak memory 196452 kb
Host smart-0d1601e0-45cf-48fa-ba6d-05f3317daa48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497914642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2497914642
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.457032201
Short name T669
Test name
Test status
Simulation time 148830647 ps
CPU time 1.16 seconds
Started Jul 28 05:14:16 PM PDT 24
Finished Jul 28 05:14:17 PM PDT 24
Peak memory 196564 kb
Host smart-ee990d31-f904-4982-ba49-d432d023bd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457032201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.457032201
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3077208613
Short name T532
Test name
Test status
Simulation time 196052568 ps
CPU time 1.19 seconds
Started Jul 28 05:14:05 PM PDT 24
Finished Jul 28 05:14:07 PM PDT 24
Peak memory 198552 kb
Host smart-9ba29145-53f6-4966-9c1a-6788f883c058
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077208613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3077208613
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3309430131
Short name T680
Test name
Test status
Simulation time 393766477 ps
CPU time 4.79 seconds
Started Jul 28 05:14:20 PM PDT 24
Finished Jul 28 05:14:25 PM PDT 24
Peak memory 198456 kb
Host smart-7a0a6f2a-108d-40e6-9a19-21dc69045e20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309430131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3309430131
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3988442158
Short name T105
Test name
Test status
Simulation time 44921246 ps
CPU time 1.25 seconds
Started Jul 28 05:14:09 PM PDT 24
Finished Jul 28 05:14:10 PM PDT 24
Peak memory 196004 kb
Host smart-38e94a5a-0472-49f4-9e20-cb5a4ce32544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988442158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3988442158
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.379235935
Short name T688
Test name
Test status
Simulation time 361246130 ps
CPU time 1 seconds
Started Jul 28 05:14:10 PM PDT 24
Finished Jul 28 05:14:11 PM PDT 24
Peak memory 196796 kb
Host smart-a57d17a6-2364-4673-ad17-4e9d3efb2105
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379235935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.379235935
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.4268536774
Short name T239
Test name
Test status
Simulation time 28072936515 ps
CPU time 179.06 seconds
Started Jul 28 05:14:19 PM PDT 24
Finished Jul 28 05:17:18 PM PDT 24
Peak memory 198580 kb
Host smart-248ba4d8-2f3a-45e4-9ccc-2feb81dd5f3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268536774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.4268536774
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.3842565014
Short name T51
Test name
Test status
Simulation time 13812045944 ps
CPU time 448.08 seconds
Started Jul 28 05:14:11 PM PDT 24
Finished Jul 28 05:21:40 PM PDT 24
Peak memory 198764 kb
Host smart-7c514af8-4e27-46be-a4f0-85437beae224
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3842565014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.3842565014
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2008986204
Short name T362
Test name
Test status
Simulation time 26993484 ps
CPU time 0.58 seconds
Started Jul 28 05:14:29 PM PDT 24
Finished Jul 28 05:14:30 PM PDT 24
Peak memory 194520 kb
Host smart-c30bce9d-db51-43bd-b117-8ec17b27d9a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008986204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2008986204
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1982708515
Short name T394
Test name
Test status
Simulation time 115484868 ps
CPU time 0.88 seconds
Started Jul 28 05:14:12 PM PDT 24
Finished Jul 28 05:14:13 PM PDT 24
Peak memory 196780 kb
Host smart-c9e00cf8-badd-48b1-9bc9-1479126a071a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982708515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1982708515
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3646925370
Short name T331
Test name
Test status
Simulation time 523338812 ps
CPU time 14.54 seconds
Started Jul 28 05:14:18 PM PDT 24
Finished Jul 28 05:14:33 PM PDT 24
Peak memory 198504 kb
Host smart-6cdbbb9a-745b-4c46-bf1e-72ca526b1cbd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646925370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3646925370
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1241872356
Short name T275
Test name
Test status
Simulation time 67684918 ps
CPU time 0.98 seconds
Started Jul 28 05:14:11 PM PDT 24
Finished Jul 28 05:14:12 PM PDT 24
Peak memory 196972 kb
Host smart-77e4cb0d-de85-4f92-b328-18912134babc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241872356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1241872356
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3250206931
Short name T12
Test name
Test status
Simulation time 32551681 ps
CPU time 0.98 seconds
Started Jul 28 05:14:13 PM PDT 24
Finished Jul 28 05:14:14 PM PDT 24
Peak memory 196320 kb
Host smart-3db33fa1-021f-4409-95da-b9a1568ef15d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250206931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3250206931
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3995520000
Short name T292
Test name
Test status
Simulation time 45453569 ps
CPU time 1 seconds
Started Jul 28 05:14:24 PM PDT 24
Finished Jul 28 05:14:25 PM PDT 24
Peak memory 196572 kb
Host smart-68a38029-5fc1-48e5-9147-0420bfda9250
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995520000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3995520000
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.679233377
Short name T408
Test name
Test status
Simulation time 463268934 ps
CPU time 3.39 seconds
Started Jul 28 05:14:11 PM PDT 24
Finished Jul 28 05:14:15 PM PDT 24
Peak memory 196256 kb
Host smart-c2ac66c5-e0ad-4761-b87e-d852073899d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679233377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
679233377
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1506081729
Short name T319
Test name
Test status
Simulation time 39399563 ps
CPU time 0.62 seconds
Started Jul 28 05:14:11 PM PDT 24
Finished Jul 28 05:14:11 PM PDT 24
Peak memory 194700 kb
Host smart-cb2f1e56-531c-4885-8e0c-767053d02186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506081729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1506081729
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.2681863525
Short name T479
Test name
Test status
Simulation time 79662596 ps
CPU time 0.9 seconds
Started Jul 28 05:14:16 PM PDT 24
Finished Jul 28 05:14:17 PM PDT 24
Peak memory 196340 kb
Host smart-44bce256-df97-4de5-88c7-13b62f22e2fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681863525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.2681863525
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.136884007
Short name T379
Test name
Test status
Simulation time 123480666 ps
CPU time 3.84 seconds
Started Jul 28 05:14:11 PM PDT 24
Finished Jul 28 05:14:15 PM PDT 24
Peak memory 198444 kb
Host smart-54ca39e6-48e0-4d10-8f72-b679373baa6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136884007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.136884007
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1954634248
Short name T651
Test name
Test status
Simulation time 134458057 ps
CPU time 1.18 seconds
Started Jul 28 05:14:15 PM PDT 24
Finished Jul 28 05:14:16 PM PDT 24
Peak memory 196948 kb
Host smart-3161dcb2-b6d4-4f51-9c24-71dadd5ce605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954634248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1954634248
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.333012926
Short name T460
Test name
Test status
Simulation time 151684010 ps
CPU time 1.34 seconds
Started Jul 28 05:14:18 PM PDT 24
Finished Jul 28 05:14:20 PM PDT 24
Peak memory 197228 kb
Host smart-e94227d1-c532-4561-8252-9a314b85b78a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333012926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.333012926
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.2152304811
Short name T14
Test name
Test status
Simulation time 2571516743 ps
CPU time 65.54 seconds
Started Jul 28 05:14:08 PM PDT 24
Finished Jul 28 05:15:13 PM PDT 24
Peak memory 198616 kb
Host smart-1de767ea-2554-4ebb-b673-8fa3d92226f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152304811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.2152304811
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2514041881
Short name T521
Test name
Test status
Simulation time 24308565 ps
CPU time 0.57 seconds
Started Jul 28 05:14:24 PM PDT 24
Finished Jul 28 05:14:25 PM PDT 24
Peak memory 194432 kb
Host smart-7a275f96-9484-4b5c-ae94-9757b73a6fac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514041881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2514041881
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3397757270
Short name T400
Test name
Test status
Simulation time 22464084 ps
CPU time 0.58 seconds
Started Jul 28 05:14:30 PM PDT 24
Finished Jul 28 05:14:31 PM PDT 24
Peak memory 194304 kb
Host smart-2a355b5e-a036-4ea9-ba1c-8f89be04a284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397757270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3397757270
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.2613612624
Short name T412
Test name
Test status
Simulation time 1453248714 ps
CPU time 14.31 seconds
Started Jul 28 05:14:28 PM PDT 24
Finished Jul 28 05:14:42 PM PDT 24
Peak memory 197328 kb
Host smart-c378f702-5d2d-4510-aebb-f2ca36e3609a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613612624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.2613612624
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.4156559183
Short name T393
Test name
Test status
Simulation time 112409455 ps
CPU time 0.84 seconds
Started Jul 28 05:14:26 PM PDT 24
Finished Jul 28 05:14:27 PM PDT 24
Peak memory 196484 kb
Host smart-6bf3e581-d6cd-4f6a-aa59-d463972f8f63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156559183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.4156559183
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2630424238
Short name T294
Test name
Test status
Simulation time 154644276 ps
CPU time 1.16 seconds
Started Jul 28 05:14:21 PM PDT 24
Finished Jul 28 05:14:22 PM PDT 24
Peak memory 196304 kb
Host smart-a33d58c6-f31d-48f3-b4fa-4b529e55281e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630424238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2630424238
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3517505674
Short name T270
Test name
Test status
Simulation time 295804574 ps
CPU time 3 seconds
Started Jul 28 05:14:29 PM PDT 24
Finished Jul 28 05:14:32 PM PDT 24
Peak memory 198612 kb
Host smart-8a3d2223-d28e-4dc2-bde3-5a5623a27661
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517505674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3517505674
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.2582785920
Short name T179
Test name
Test status
Simulation time 187621349 ps
CPU time 1.27 seconds
Started Jul 28 05:14:16 PM PDT 24
Finished Jul 28 05:14:17 PM PDT 24
Peak memory 197260 kb
Host smart-e1aa933a-d02d-4c0c-af80-36c464f64950
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582785920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.2582785920
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3491036197
Short name T382
Test name
Test status
Simulation time 18941969 ps
CPU time 0.69 seconds
Started Jul 28 05:14:30 PM PDT 24
Finished Jul 28 05:14:31 PM PDT 24
Peak memory 196056 kb
Host smart-80433a57-91b6-4b14-8263-e698f361832f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491036197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3491036197
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3984543847
Short name T402
Test name
Test status
Simulation time 112068306 ps
CPU time 0.95 seconds
Started Jul 28 05:14:18 PM PDT 24
Finished Jul 28 05:14:19 PM PDT 24
Peak memory 196520 kb
Host smart-82fc3e0d-a9bd-42a4-9688-b59560d293e1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984543847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3984543847
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.377387113
Short name T474
Test name
Test status
Simulation time 1474028401 ps
CPU time 4.83 seconds
Started Jul 28 05:14:25 PM PDT 24
Finished Jul 28 05:14:30 PM PDT 24
Peak memory 198388 kb
Host smart-fc464b33-4158-495c-927f-792465f3c4fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377387113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ran
dom_long_reg_writes_reg_reads.377387113
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2569179640
Short name T83
Test name
Test status
Simulation time 16991998 ps
CPU time 0.69 seconds
Started Jul 28 05:14:30 PM PDT 24
Finished Jul 28 05:14:30 PM PDT 24
Peak memory 195360 kb
Host smart-3384f160-1662-4641-848b-cdc8fccc3690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569179640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2569179640
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2978203017
Short name T579
Test name
Test status
Simulation time 118556440 ps
CPU time 1.07 seconds
Started Jul 28 05:14:26 PM PDT 24
Finished Jul 28 05:14:27 PM PDT 24
Peak memory 196268 kb
Host smart-e813942e-8553-4a53-9759-34f3c8f33371
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978203017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2978203017
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1632140570
Short name T107
Test name
Test status
Simulation time 25770806208 ps
CPU time 179.14 seconds
Started Jul 28 05:14:28 PM PDT 24
Finished Jul 28 05:17:27 PM PDT 24
Peak memory 198604 kb
Host smart-3e42c04c-ad08-4d6d-a26f-fcfd709b10d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632140570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1632140570
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.3897126173
Short name T52
Test name
Test status
Simulation time 98252824394 ps
CPU time 717.32 seconds
Started Jul 28 05:14:28 PM PDT 24
Finished Jul 28 05:26:25 PM PDT 24
Peak memory 198696 kb
Host smart-b257a63c-0270-4e31-8bb7-8bf9260be0f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3897126173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.3897126173
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.560120479
Short name T169
Test name
Test status
Simulation time 47270498 ps
CPU time 0.56 seconds
Started Jul 28 05:14:30 PM PDT 24
Finished Jul 28 05:14:31 PM PDT 24
Peak memory 194424 kb
Host smart-d4c4b8b4-14f8-4b84-ba77-791552d647d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560120479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.560120479
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2400222431
Short name T372
Test name
Test status
Simulation time 21339937 ps
CPU time 0.72 seconds
Started Jul 28 05:14:19 PM PDT 24
Finished Jul 28 05:14:20 PM PDT 24
Peak memory 196392 kb
Host smart-52fb9ef2-6201-4c3a-b2e6-e66dc29c9088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400222431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2400222431
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.4210066683
Short name T654
Test name
Test status
Simulation time 336833446 ps
CPU time 9.07 seconds
Started Jul 28 05:14:28 PM PDT 24
Finished Jul 28 05:14:38 PM PDT 24
Peak memory 197188 kb
Host smart-1482d7f4-5b1a-4b9e-9d18-7b805eac7d18
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210066683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.4210066683
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2177212772
Short name T418
Test name
Test status
Simulation time 52757675 ps
CPU time 0.8 seconds
Started Jul 28 05:14:15 PM PDT 24
Finished Jul 28 05:14:16 PM PDT 24
Peak memory 196420 kb
Host smart-9074f6ec-426e-43da-b2fe-80432f278c4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177212772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2177212772
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.4038843718
Short name T686
Test name
Test status
Simulation time 40935222 ps
CPU time 0.77 seconds
Started Jul 28 05:14:24 PM PDT 24
Finished Jul 28 05:14:25 PM PDT 24
Peak memory 195844 kb
Host smart-0d666d51-2cc3-40c1-9b79-f6fe25e0c15b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038843718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.4038843718
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1108773256
Short name T96
Test name
Test status
Simulation time 336877852 ps
CPU time 3.3 seconds
Started Jul 28 05:14:18 PM PDT 24
Finished Jul 28 05:14:21 PM PDT 24
Peak memory 198680 kb
Host smart-a7bd3f3a-765f-4be1-9589-3e23780d650e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108773256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1108773256
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.1826636159
Short name T226
Test name
Test status
Simulation time 90755360 ps
CPU time 1.17 seconds
Started Jul 28 05:14:28 PM PDT 24
Finished Jul 28 05:14:29 PM PDT 24
Peak memory 196860 kb
Host smart-9f7399d5-469b-4d4f-bb1f-6af6b4657b70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826636159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.1826636159
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.456861712
Short name T265
Test name
Test status
Simulation time 100867692 ps
CPU time 0.88 seconds
Started Jul 28 05:14:31 PM PDT 24
Finished Jul 28 05:14:32 PM PDT 24
Peak memory 197056 kb
Host smart-e632f7f8-98d5-4209-b6d1-56baa32409d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456861712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.456861712
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.1928433467
Short name T212
Test name
Test status
Simulation time 36263101 ps
CPU time 1.18 seconds
Started Jul 28 05:14:28 PM PDT 24
Finished Jul 28 05:14:30 PM PDT 24
Peak memory 197532 kb
Host smart-79353d99-40ff-4286-8fa3-6045a341a699
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928433467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.1928433467
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2932406197
Short name T642
Test name
Test status
Simulation time 3572504583 ps
CPU time 5.24 seconds
Started Jul 28 05:14:24 PM PDT 24
Finished Jul 28 05:14:30 PM PDT 24
Peak memory 198556 kb
Host smart-748a8a06-4684-4860-8ff7-a481aa6fa588
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932406197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.2932406197
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.386874744
Short name T287
Test name
Test status
Simulation time 75057021 ps
CPU time 1.66 seconds
Started Jul 28 05:14:19 PM PDT 24
Finished Jul 28 05:14:21 PM PDT 24
Peak memory 197280 kb
Host smart-2c90d39d-e51a-4c39-81ea-26ccfde3d8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386874744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.386874744
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.1934902756
Short name T689
Test name
Test status
Simulation time 67308500 ps
CPU time 1.2 seconds
Started Jul 28 05:14:15 PM PDT 24
Finished Jul 28 05:14:16 PM PDT 24
Peak memory 196288 kb
Host smart-fac8ed67-acb5-4067-ada6-082f341ab337
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934902756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.1934902756
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.4238090254
Short name T128
Test name
Test status
Simulation time 6282622670 ps
CPU time 35.79 seconds
Started Jul 28 05:14:27 PM PDT 24
Finished Jul 28 05:15:03 PM PDT 24
Peak memory 198684 kb
Host smart-6483e7f3-f452-4cfc-bf63-dfd5f70c0051
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238090254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.4238090254
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.962775069
Short name T3
Test name
Test status
Simulation time 58745023915 ps
CPU time 748.26 seconds
Started Jul 28 05:14:16 PM PDT 24
Finished Jul 28 05:26:44 PM PDT 24
Peak memory 198744 kb
Host smart-0f0ab484-e0b3-433e-9ce6-bab885ca3999
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=962775069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.962775069
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1908264601
Short name T35
Test name
Test status
Simulation time 39004229 ps
CPU time 0.57 seconds
Started Jul 28 05:14:19 PM PDT 24
Finished Jul 28 05:14:20 PM PDT 24
Peak memory 195132 kb
Host smart-3dd7f69d-bd8c-4c6a-ad49-58810dc52d11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908264601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1908264601
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2072040506
Short name T368
Test name
Test status
Simulation time 18642152 ps
CPU time 0.68 seconds
Started Jul 28 05:14:19 PM PDT 24
Finished Jul 28 05:14:20 PM PDT 24
Peak memory 195640 kb
Host smart-a43fd044-bd90-4fa5-b688-0be8fb533ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072040506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2072040506
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.361459064
Short name T118
Test name
Test status
Simulation time 874584080 ps
CPU time 8.56 seconds
Started Jul 28 05:14:24 PM PDT 24
Finished Jul 28 05:14:32 PM PDT 24
Peak memory 198436 kb
Host smart-8ea40db7-1c1a-4cd6-bc65-edf694fe0937
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361459064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.361459064
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1986381645
Short name T151
Test name
Test status
Simulation time 128512956 ps
CPU time 0.76 seconds
Started Jul 28 05:14:22 PM PDT 24
Finished Jul 28 05:14:23 PM PDT 24
Peak memory 197040 kb
Host smart-11c4ef75-de05-492d-8677-17c0e7593c93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986381645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1986381645
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.53069444
Short name T554
Test name
Test status
Simulation time 468577833 ps
CPU time 1.14 seconds
Started Jul 28 05:14:25 PM PDT 24
Finished Jul 28 05:14:26 PM PDT 24
Peak memory 196608 kb
Host smart-811ec62e-9886-48c9-be74-28258783659b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53069444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.53069444
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1833627778
Short name T628
Test name
Test status
Simulation time 77656144 ps
CPU time 2.74 seconds
Started Jul 28 05:14:19 PM PDT 24
Finished Jul 28 05:14:22 PM PDT 24
Peak memory 198484 kb
Host smart-9f70a07b-99ad-40b3-aa00-547cc3f7142c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833627778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1833627778
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2695802330
Short name T440
Test name
Test status
Simulation time 317923141 ps
CPU time 2.47 seconds
Started Jul 28 05:14:23 PM PDT 24
Finished Jul 28 05:14:25 PM PDT 24
Peak memory 198604 kb
Host smart-df57023e-2074-4b3a-97b0-da40c7c3a9fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695802330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2695802330
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.1527096883
Short name T432
Test name
Test status
Simulation time 25159502 ps
CPU time 0.68 seconds
Started Jul 28 05:14:18 PM PDT 24
Finished Jul 28 05:14:19 PM PDT 24
Peak memory 194704 kb
Host smart-e600307d-96e1-440a-a0f5-6c4f0b9b8b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527096883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.1527096883
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3592820952
Short name T332
Test name
Test status
Simulation time 31910012 ps
CPU time 0.91 seconds
Started Jul 28 05:14:22 PM PDT 24
Finished Jul 28 05:14:23 PM PDT 24
Peak memory 197112 kb
Host smart-59ced916-d204-4833-abcf-0ff5ae58293b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592820952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3592820952
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1557736169
Short name T370
Test name
Test status
Simulation time 70973380 ps
CPU time 2.58 seconds
Started Jul 28 05:14:29 PM PDT 24
Finished Jul 28 05:14:32 PM PDT 24
Peak memory 198484 kb
Host smart-670923f7-aab9-4451-8f09-8330b732d7a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557736169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1557736169
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.306257080
Short name T100
Test name
Test status
Simulation time 149060255 ps
CPU time 1.11 seconds
Started Jul 28 05:14:22 PM PDT 24
Finished Jul 28 05:14:23 PM PDT 24
Peak memory 196256 kb
Host smart-a2581167-853e-4ab1-ab01-009be334a429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306257080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.306257080
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.1365784248
Short name T237
Test name
Test status
Simulation time 55083358 ps
CPU time 0.96 seconds
Started Jul 28 05:14:23 PM PDT 24
Finished Jul 28 05:14:24 PM PDT 24
Peak memory 195812 kb
Host smart-2cc581e1-fd3f-439f-bb28-21bd95af01ba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365784248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.1365784248
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.4002552491
Short name T477
Test name
Test status
Simulation time 19612653184 ps
CPU time 102.11 seconds
Started Jul 28 05:14:25 PM PDT 24
Finished Jul 28 05:16:08 PM PDT 24
Peak memory 198556 kb
Host smart-ce570a65-6fcf-4071-8375-89787a42d6f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002552491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.4002552491
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.437286928
Short name T584
Test name
Test status
Simulation time 95093455967 ps
CPU time 619.95 seconds
Started Jul 28 05:14:25 PM PDT 24
Finished Jul 28 05:24:45 PM PDT 24
Peak memory 198780 kb
Host smart-3748aae0-f284-4f07-91df-6f50893d10b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=437286928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.437286928
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.889293932
Short name T672
Test name
Test status
Simulation time 11722695 ps
CPU time 0.57 seconds
Started Jul 28 05:14:32 PM PDT 24
Finished Jul 28 05:14:33 PM PDT 24
Peak memory 195120 kb
Host smart-62308ba0-111b-444e-bc24-bb2b83a173bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889293932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.889293932
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.680238109
Short name T97
Test name
Test status
Simulation time 39674131 ps
CPU time 0.84 seconds
Started Jul 28 05:14:34 PM PDT 24
Finished Jul 28 05:14:35 PM PDT 24
Peak memory 196860 kb
Host smart-2103cd09-b0d9-4884-bf01-5b93b813d93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680238109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.680238109
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1076159330
Short name T227
Test name
Test status
Simulation time 262964507 ps
CPU time 3.26 seconds
Started Jul 28 05:14:29 PM PDT 24
Finished Jul 28 05:14:32 PM PDT 24
Peak memory 196932 kb
Host smart-f951048b-18e6-4bb3-8f9a-134ef5aeefb6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076159330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1076159330
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.4104171983
Short name T509
Test name
Test status
Simulation time 457400094 ps
CPU time 0.93 seconds
Started Jul 28 05:14:36 PM PDT 24
Finished Jul 28 05:14:37 PM PDT 24
Peak memory 197700 kb
Host smart-44f7fe02-a817-4eaf-85cb-79fb83174810
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104171983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.4104171983
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.527967855
Short name T365
Test name
Test status
Simulation time 343067098 ps
CPU time 1.35 seconds
Started Jul 28 05:14:28 PM PDT 24
Finished Jul 28 05:14:29 PM PDT 24
Peak memory 196584 kb
Host smart-81a9e5a8-451e-4d25-abfe-8b1514b93ea5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527967855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.527967855
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2893381671
Short name T271
Test name
Test status
Simulation time 525001830 ps
CPU time 2.89 seconds
Started Jul 28 05:14:27 PM PDT 24
Finished Jul 28 05:14:30 PM PDT 24
Peak memory 196920 kb
Host smart-a08fd915-ca4e-49a9-be4f-34dde604eca4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893381671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2893381671
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.606286850
Short name T263
Test name
Test status
Simulation time 28898745 ps
CPU time 0.93 seconds
Started Jul 28 05:14:35 PM PDT 24
Finished Jul 28 05:14:36 PM PDT 24
Peak memory 196052 kb
Host smart-51ec45a0-e985-4d71-b0cc-23c0b35e9f54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606286850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
606286850
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1127484891
Short name T380
Test name
Test status
Simulation time 131967620 ps
CPU time 0.9 seconds
Started Jul 28 05:14:28 PM PDT 24
Finished Jul 28 05:14:29 PM PDT 24
Peak memory 196524 kb
Host smart-039e0374-e8ad-480f-9387-ab8f04fb051d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127484891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1127484891
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2742710270
Short name T452
Test name
Test status
Simulation time 36023031 ps
CPU time 0.92 seconds
Started Jul 28 05:14:28 PM PDT 24
Finished Jul 28 05:14:29 PM PDT 24
Peak memory 196692 kb
Host smart-3923c074-0ecf-486b-b59d-a40ed89a9844
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742710270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2742710270
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3355586745
Short name T414
Test name
Test status
Simulation time 564915846 ps
CPU time 4.34 seconds
Started Jul 28 05:14:22 PM PDT 24
Finished Jul 28 05:14:27 PM PDT 24
Peak memory 198416 kb
Host smart-5b97b7ee-e657-4c33-b124-2c7e3d39af3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355586745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3355586745
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.3900812849
Short name T199
Test name
Test status
Simulation time 20495981 ps
CPU time 0.76 seconds
Started Jul 28 05:14:18 PM PDT 24
Finished Jul 28 05:14:18 PM PDT 24
Peak memory 196512 kb
Host smart-9626d03a-67e1-42c0-a3ae-59331e08fe68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900812849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.3900812849
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2049212118
Short name T357
Test name
Test status
Simulation time 39745784 ps
CPU time 1.17 seconds
Started Jul 28 05:14:30 PM PDT 24
Finished Jul 28 05:14:31 PM PDT 24
Peak memory 197396 kb
Host smart-1dbf464c-eb1d-4676-a171-72d97e33ba0e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049212118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2049212118
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.332070231
Short name T315
Test name
Test status
Simulation time 11223872275 ps
CPU time 137.65 seconds
Started Jul 28 05:14:31 PM PDT 24
Finished Jul 28 05:16:49 PM PDT 24
Peak memory 198656 kb
Host smart-c8ec565a-0621-4dda-a8ea-26c721d525d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332070231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.g
pio_stress_all.332070231
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.3632027701
Short name T671
Test name
Test status
Simulation time 15853358864 ps
CPU time 213.31 seconds
Started Jul 28 05:14:18 PM PDT 24
Finished Jul 28 05:17:51 PM PDT 24
Peak memory 198912 kb
Host smart-12ece276-5107-450d-a45b-88ded6d8c8bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3632027701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.3632027701
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1335308025
Short name T471
Test name
Test status
Simulation time 98259313 ps
CPU time 0.57 seconds
Started Jul 28 05:14:32 PM PDT 24
Finished Jul 28 05:14:33 PM PDT 24
Peak memory 194612 kb
Host smart-1bb06f7e-a5b1-4a8f-a59a-b4b93abfd801
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335308025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1335308025
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2900983258
Short name T127
Test name
Test status
Simulation time 174013469 ps
CPU time 0.7 seconds
Started Jul 28 05:14:21 PM PDT 24
Finished Jul 28 05:14:21 PM PDT 24
Peak memory 194620 kb
Host smart-de873a24-8c92-4fb5-a241-cafe24c360b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900983258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2900983258
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.222494412
Short name T203
Test name
Test status
Simulation time 2217592178 ps
CPU time 18.68 seconds
Started Jul 28 05:14:29 PM PDT 24
Finished Jul 28 05:14:48 PM PDT 24
Peak memory 197484 kb
Host smart-18e00f94-7b51-4205-96fa-057bfa6287df
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222494412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.222494412
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2522327043
Short name T348
Test name
Test status
Simulation time 121209441 ps
CPU time 0.99 seconds
Started Jul 28 05:14:35 PM PDT 24
Finished Jul 28 05:14:36 PM PDT 24
Peak memory 197020 kb
Host smart-398523f3-9818-4319-884b-30a2aa8aba22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522327043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2522327043
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.3598615367
Short name T541
Test name
Test status
Simulation time 37106819 ps
CPU time 0.85 seconds
Started Jul 28 05:14:38 PM PDT 24
Finished Jul 28 05:14:39 PM PDT 24
Peak memory 196068 kb
Host smart-1a21f065-051a-4adc-be97-ccea4ab63a06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598615367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.3598615367
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2704138288
Short name T202
Test name
Test status
Simulation time 81990682 ps
CPU time 3.38 seconds
Started Jul 28 05:14:34 PM PDT 24
Finished Jul 28 05:14:38 PM PDT 24
Peak memory 198648 kb
Host smart-b5aa7721-38cf-4cf9-9177-df17766d594a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704138288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2704138288
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.4059258782
Short name T524
Test name
Test status
Simulation time 36627574 ps
CPU time 1.25 seconds
Started Jul 28 05:14:18 PM PDT 24
Finished Jul 28 05:14:20 PM PDT 24
Peak memory 196632 kb
Host smart-23eb0494-4ce4-4928-bcc5-49d9f22ffb7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059258782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.4059258782
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.545140733
Short name T410
Test name
Test status
Simulation time 79129880 ps
CPU time 1.12 seconds
Started Jul 28 05:14:34 PM PDT 24
Finished Jul 28 05:14:36 PM PDT 24
Peak memory 197140 kb
Host smart-20e86978-752c-4971-9c3c-f0e7ce99bc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545140733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.545140733
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1855497285
Short name T124
Test name
Test status
Simulation time 66855947 ps
CPU time 1.19 seconds
Started Jul 28 05:14:25 PM PDT 24
Finished Jul 28 05:14:26 PM PDT 24
Peak memory 197400 kb
Host smart-87a49303-ec2c-4e84-98c8-7b6bdb7bd79a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855497285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.1855497285
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.529482459
Short name T676
Test name
Test status
Simulation time 211820227 ps
CPU time 4.67 seconds
Started Jul 28 05:14:24 PM PDT 24
Finished Jul 28 05:14:29 PM PDT 24
Peak memory 198440 kb
Host smart-3bdfc7a3-bdff-4cc4-9292-f44bfa7f20b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529482459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ran
dom_long_reg_writes_reg_reads.529482459
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1908421437
Short name T421
Test name
Test status
Simulation time 32178027 ps
CPU time 0.9 seconds
Started Jul 28 05:14:29 PM PDT 24
Finished Jul 28 05:14:33 PM PDT 24
Peak memory 195740 kb
Host smart-acfc1a4e-762b-4c6b-ac8f-bb12bf77192d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908421437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1908421437
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.4184344044
Short name T603
Test name
Test status
Simulation time 187380906 ps
CPU time 0.95 seconds
Started Jul 28 05:14:29 PM PDT 24
Finished Jul 28 05:14:30 PM PDT 24
Peak memory 196260 kb
Host smart-7fef1070-06d5-4d11-a283-1ac783ca2c7d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184344044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.4184344044
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2024512444
Short name T159
Test name
Test status
Simulation time 101583888258 ps
CPU time 177.1 seconds
Started Jul 28 05:14:18 PM PDT 24
Finished Jul 28 05:17:15 PM PDT 24
Peak memory 198788 kb
Host smart-a077135a-5add-4cf6-b9d2-e98e335e1187
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024512444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2024512444
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.49035712
Short name T638
Test name
Test status
Simulation time 13124648 ps
CPU time 0.56 seconds
Started Jul 28 05:13:37 PM PDT 24
Finished Jul 28 05:13:38 PM PDT 24
Peak memory 194628 kb
Host smart-7e917076-4d25-4499-9202-3f6bddb227a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49035712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.49035712
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1651463623
Short name T627
Test name
Test status
Simulation time 31376623 ps
CPU time 0.78 seconds
Started Jul 28 05:13:33 PM PDT 24
Finished Jul 28 05:13:34 PM PDT 24
Peak memory 195964 kb
Host smart-a5ec006c-8aae-494e-8fb4-7de09c30eebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651463623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1651463623
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3003681339
Short name T167
Test name
Test status
Simulation time 370560856 ps
CPU time 8.12 seconds
Started Jul 28 05:13:33 PM PDT 24
Finished Jul 28 05:13:42 PM PDT 24
Peak memory 197296 kb
Host smart-b4446fbd-16d3-4e34-bb7c-73bcc8990dea
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003681339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3003681339
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2330613812
Short name T580
Test name
Test status
Simulation time 344756793 ps
CPU time 0.91 seconds
Started Jul 28 05:13:41 PM PDT 24
Finished Jul 28 05:13:42 PM PDT 24
Peak memory 197692 kb
Host smart-0971787d-935a-48ae-8ce3-7a01b964bcef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330613812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2330613812
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3967847704
Short name T122
Test name
Test status
Simulation time 69672868 ps
CPU time 1.09 seconds
Started Jul 28 05:13:32 PM PDT 24
Finished Jul 28 05:13:34 PM PDT 24
Peak memory 196648 kb
Host smart-e638b1bc-634b-4bf6-b474-83e0acda84cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967847704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3967847704
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1026537653
Short name T91
Test name
Test status
Simulation time 127654563 ps
CPU time 2.45 seconds
Started Jul 28 05:13:36 PM PDT 24
Finished Jul 28 05:13:39 PM PDT 24
Peak memory 196996 kb
Host smart-00f6298c-a43a-4d89-bd47-bd8ddc174415
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026537653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1026537653
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2823823718
Short name T506
Test name
Test status
Simulation time 40585518 ps
CPU time 1.41 seconds
Started Jul 28 05:13:34 PM PDT 24
Finished Jul 28 05:13:36 PM PDT 24
Peak memory 197096 kb
Host smart-09299727-cb13-4660-b926-0b21fd5fd259
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823823718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2823823718
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.203263817
Short name T407
Test name
Test status
Simulation time 127558333 ps
CPU time 1.26 seconds
Started Jul 28 05:13:32 PM PDT 24
Finished Jul 28 05:13:34 PM PDT 24
Peak memory 198484 kb
Host smart-875602d9-536c-48ee-a982-1304b0e38a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203263817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.203263817
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3135058950
Short name T556
Test name
Test status
Simulation time 35426680 ps
CPU time 1.15 seconds
Started Jul 28 05:13:29 PM PDT 24
Finished Jul 28 05:13:31 PM PDT 24
Peak memory 196300 kb
Host smart-c77aecc5-a338-4d1a-ba42-a684104aff7c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135058950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3135058950
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1664519627
Short name T139
Test name
Test status
Simulation time 942017661 ps
CPU time 5.24 seconds
Started Jul 28 05:13:34 PM PDT 24
Finished Jul 28 05:13:40 PM PDT 24
Peak memory 198488 kb
Host smart-0eea2c59-b7cc-4b11-83c0-88ff920a5387
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664519627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.1664519627
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.74985760
Short name T34
Test name
Test status
Simulation time 55862624 ps
CPU time 0.9 seconds
Started Jul 28 05:13:45 PM PDT 24
Finished Jul 28 05:13:46 PM PDT 24
Peak memory 214432 kb
Host smart-31e5135d-0ccd-4350-8349-4d58a638c8e1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74985760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.74985760
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.281832035
Short name T108
Test name
Test status
Simulation time 219194630 ps
CPU time 0.98 seconds
Started Jul 28 05:13:38 PM PDT 24
Finished Jul 28 05:13:40 PM PDT 24
Peak memory 196380 kb
Host smart-7e5bca26-b5c0-4cc1-ae9b-b495949cfde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281832035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.281832035
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.224153204
Short name T485
Test name
Test status
Simulation time 202578270 ps
CPU time 1.14 seconds
Started Jul 28 05:13:34 PM PDT 24
Finished Jul 28 05:13:35 PM PDT 24
Peak memory 196908 kb
Host smart-f5f7a948-8177-401d-bf26-29230174a799
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224153204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.224153204
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.821681976
Short name T175
Test name
Test status
Simulation time 4872182170 ps
CPU time 50.71 seconds
Started Jul 28 05:13:36 PM PDT 24
Finished Jul 28 05:14:27 PM PDT 24
Peak memory 198584 kb
Host smart-e74a229b-70d2-48fb-ab82-e713d5ab4a05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821681976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gp
io_stress_all.821681976
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.2703456778
Short name T545
Test name
Test status
Simulation time 33065506756 ps
CPU time 918.35 seconds
Started Jul 28 05:13:34 PM PDT 24
Finished Jul 28 05:28:54 PM PDT 24
Peak memory 198736 kb
Host smart-c7847019-8010-4847-b17d-a48e36a5a640
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2703456778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.2703456778
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.4011957803
Short name T425
Test name
Test status
Simulation time 22121569 ps
CPU time 0.57 seconds
Started Jul 28 05:14:31 PM PDT 24
Finished Jul 28 05:14:32 PM PDT 24
Peak memory 194400 kb
Host smart-85715946-9dff-4cbd-aa5a-cbb64c719f0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011957803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.4011957803
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.401442243
Short name T235
Test name
Test status
Simulation time 54091077 ps
CPU time 0.61 seconds
Started Jul 28 05:14:27 PM PDT 24
Finished Jul 28 05:14:27 PM PDT 24
Peak memory 195128 kb
Host smart-c8721aac-df66-4e99-907a-b7925ba425be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401442243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.401442243
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3177620786
Short name T403
Test name
Test status
Simulation time 466171218 ps
CPU time 7.11 seconds
Started Jul 28 05:14:27 PM PDT 24
Finished Jul 28 05:14:35 PM PDT 24
Peak memory 197340 kb
Host smart-7bcdd077-74f5-4889-b86b-643c412f8b70
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177620786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3177620786
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2474884314
Short name T678
Test name
Test status
Simulation time 24250146 ps
CPU time 0.61 seconds
Started Jul 28 05:14:25 PM PDT 24
Finished Jul 28 05:14:26 PM PDT 24
Peak memory 194816 kb
Host smart-754f95b1-5339-4d5b-8a90-416539602b53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474884314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2474884314
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2431978951
Short name T216
Test name
Test status
Simulation time 167374388 ps
CPU time 1.27 seconds
Started Jul 28 05:14:29 PM PDT 24
Finished Jul 28 05:14:30 PM PDT 24
Peak memory 197700 kb
Host smart-1d2532a1-102e-4422-93a5-599eb9dbc226
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431978951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2431978951
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3148923792
Short name T260
Test name
Test status
Simulation time 59364038 ps
CPU time 2.27 seconds
Started Jul 28 05:14:28 PM PDT 24
Finished Jul 28 05:14:31 PM PDT 24
Peak memory 198560 kb
Host smart-150becb0-10fa-4837-b48d-1a9fc6a90202
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148923792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3148923792
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3662265138
Short name T220
Test name
Test status
Simulation time 156226968 ps
CPU time 1.01 seconds
Started Jul 28 05:14:27 PM PDT 24
Finished Jul 28 05:14:29 PM PDT 24
Peak memory 196084 kb
Host smart-852b95b7-6adc-4e11-b155-c08623225354
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662265138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3662265138
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1854813438
Short name T435
Test name
Test status
Simulation time 127152033 ps
CPU time 1.25 seconds
Started Jul 28 05:14:22 PM PDT 24
Finished Jul 28 05:14:24 PM PDT 24
Peak memory 197052 kb
Host smart-18c71394-77c9-4051-9bf4-f911f5101eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854813438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1854813438
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.358426230
Short name T405
Test name
Test status
Simulation time 62264446 ps
CPU time 1.32 seconds
Started Jul 28 05:14:29 PM PDT 24
Finished Jul 28 05:14:31 PM PDT 24
Peak memory 197460 kb
Host smart-565aa3bd-a3b1-42fe-a29e-d79c1d629ca5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358426230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup
_pulldown.358426230
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3410895303
Short name T210
Test name
Test status
Simulation time 249942659 ps
CPU time 5.63 seconds
Started Jul 28 05:14:30 PM PDT 24
Finished Jul 28 05:14:36 PM PDT 24
Peak memory 198448 kb
Host smart-fe048552-d204-4be1-b998-64620fa45242
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410895303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3410895303
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1992743464
Short name T647
Test name
Test status
Simulation time 34621380 ps
CPU time 0.88 seconds
Started Jul 28 05:14:27 PM PDT 24
Finished Jul 28 05:14:28 PM PDT 24
Peak memory 195916 kb
Host smart-defb9250-b5ce-423f-8b90-358d5ef6a076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992743464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1992743464
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3953830054
Short name T141
Test name
Test status
Simulation time 94748109 ps
CPU time 0.89 seconds
Started Jul 28 05:14:31 PM PDT 24
Finished Jul 28 05:14:32 PM PDT 24
Peak memory 196888 kb
Host smart-c20c40ec-c4b0-465a-b5c3-b805d1c65a7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953830054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3953830054
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.569448414
Short name T224
Test name
Test status
Simulation time 4590617556 ps
CPU time 60.93 seconds
Started Jul 28 05:14:27 PM PDT 24
Finished Jul 28 05:15:28 PM PDT 24
Peak memory 198548 kb
Host smart-64d00179-9930-4a97-9d14-61114591c51f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569448414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.g
pio_stress_all.569448414
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.4047227321
Short name T586
Test name
Test status
Simulation time 56376513936 ps
CPU time 1278.2 seconds
Started Jul 28 05:14:36 PM PDT 24
Finished Jul 28 05:35:55 PM PDT 24
Peak memory 198940 kb
Host smart-e3b192d2-1274-4364-b898-61fa82967676
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4047227321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.4047227321
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.4244710828
Short name T428
Test name
Test status
Simulation time 32599160 ps
CPU time 0.58 seconds
Started Jul 28 05:14:29 PM PDT 24
Finished Jul 28 05:14:30 PM PDT 24
Peak memory 195012 kb
Host smart-58d43f42-cfc8-48b9-8d0b-fed83b4007b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244710828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.4244710828
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.296216124
Short name T232
Test name
Test status
Simulation time 75460159 ps
CPU time 0.69 seconds
Started Jul 28 05:14:29 PM PDT 24
Finished Jul 28 05:14:30 PM PDT 24
Peak memory 194524 kb
Host smart-57a6bf6f-e1a7-437d-a03d-1f091c597ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296216124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.296216124
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.2279857682
Short name T26
Test name
Test status
Simulation time 636991607 ps
CPU time 22.22 seconds
Started Jul 28 05:14:44 PM PDT 24
Finished Jul 28 05:15:07 PM PDT 24
Peak memory 198496 kb
Host smart-5bb41a98-963e-476a-b03d-3a8fa6e280c7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279857682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.2279857682
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3068124202
Short name T130
Test name
Test status
Simulation time 97628350 ps
CPU time 0.69 seconds
Started Jul 28 05:14:30 PM PDT 24
Finished Jul 28 05:14:31 PM PDT 24
Peak memory 195448 kb
Host smart-af7cf30d-31e7-4384-8bff-7f20a03c0a94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068124202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3068124202
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.1023360774
Short name T161
Test name
Test status
Simulation time 118398875 ps
CPU time 1.31 seconds
Started Jul 28 05:14:30 PM PDT 24
Finished Jul 28 05:14:32 PM PDT 24
Peak memory 197852 kb
Host smart-59740393-3952-412f-9891-423e724331ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023360774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.1023360774
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1002157301
Short name T587
Test name
Test status
Simulation time 526396400 ps
CPU time 3.57 seconds
Started Jul 28 05:14:30 PM PDT 24
Finished Jul 28 05:14:34 PM PDT 24
Peak memory 198500 kb
Host smart-ecbb0a1c-cd89-4ed9-bc2d-bede679ebef7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002157301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1002157301
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1275334632
Short name T605
Test name
Test status
Simulation time 286235196 ps
CPU time 2.08 seconds
Started Jul 28 05:14:30 PM PDT 24
Finished Jul 28 05:14:32 PM PDT 24
Peak memory 198516 kb
Host smart-a425fe79-df3d-4275-8f50-9ee4ee114c57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275334632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1275334632
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.208877768
Short name T268
Test name
Test status
Simulation time 191910671 ps
CPU time 1.11 seconds
Started Jul 28 05:14:21 PM PDT 24
Finished Jul 28 05:14:22 PM PDT 24
Peak memory 196296 kb
Host smart-90fcf9cf-17f6-4dff-a23d-5b7a94d0f3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208877768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.208877768
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2281472234
Short name T342
Test name
Test status
Simulation time 34593267 ps
CPU time 0.83 seconds
Started Jul 28 05:14:26 PM PDT 24
Finished Jul 28 05:14:27 PM PDT 24
Peak memory 197124 kb
Host smart-7ae32b9a-62d4-42de-ab0d-cdf91970e66a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281472234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2281472234
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.155931783
Short name T661
Test name
Test status
Simulation time 2051462668 ps
CPU time 6.32 seconds
Started Jul 28 05:14:26 PM PDT 24
Finished Jul 28 05:14:33 PM PDT 24
Peak memory 198392 kb
Host smart-2cda4783-9448-479f-943b-90a43cbadcba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155931783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ran
dom_long_reg_writes_reg_reads.155931783
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1487130887
Short name T406
Test name
Test status
Simulation time 63112629 ps
CPU time 1.19 seconds
Started Jul 28 05:14:30 PM PDT 24
Finished Jul 28 05:14:31 PM PDT 24
Peak memory 196236 kb
Host smart-9152b4fe-8151-4d37-8113-5adbb0e68e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487130887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1487130887
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.532357376
Short name T349
Test name
Test status
Simulation time 61452893 ps
CPU time 0.7 seconds
Started Jul 28 05:14:33 PM PDT 24
Finished Jul 28 05:14:39 PM PDT 24
Peak memory 195268 kb
Host smart-1c9e2d6d-1054-4711-b776-7a66c35d84c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532357376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.532357376
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.15438874
Short name T624
Test name
Test status
Simulation time 29880888123 ps
CPU time 219.74 seconds
Started Jul 28 05:14:27 PM PDT 24
Finished Jul 28 05:18:07 PM PDT 24
Peak memory 198572 kb
Host smart-01a253b9-66e4-454c-9e0d-d1e83a60231c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15438874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gp
io_stress_all.15438874
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.1772950436
Short name T53
Test name
Test status
Simulation time 74807885237 ps
CPU time 1737.1 seconds
Started Jul 28 05:14:35 PM PDT 24
Finished Jul 28 05:43:33 PM PDT 24
Peak memory 198716 kb
Host smart-1a713218-ba5b-41b0-b802-3fd9620f4d8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1772950436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.1772950436
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.944831439
Short name T588
Test name
Test status
Simulation time 46172493 ps
CPU time 0.57 seconds
Started Jul 28 05:14:33 PM PDT 24
Finished Jul 28 05:14:34 PM PDT 24
Peak memory 195080 kb
Host smart-0559379b-2c44-4f07-9c78-1be21406d7f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944831439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.944831439
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2274278306
Short name T195
Test name
Test status
Simulation time 35524253 ps
CPU time 0.64 seconds
Started Jul 28 05:14:33 PM PDT 24
Finished Jul 28 05:14:34 PM PDT 24
Peak memory 194608 kb
Host smart-bae46a82-7255-448c-9532-3bf6bd5c6cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274278306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2274278306
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.273989590
Short name T158
Test name
Test status
Simulation time 439048285 ps
CPU time 3.27 seconds
Started Jul 28 05:14:36 PM PDT 24
Finished Jul 28 05:14:39 PM PDT 24
Peak memory 196964 kb
Host smart-2aea9353-c0bc-4a5a-abe1-552e299ba6a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273989590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stres
s.273989590
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3732323873
Short name T114
Test name
Test status
Simulation time 154515553 ps
CPU time 0.77 seconds
Started Jul 28 05:14:31 PM PDT 24
Finished Jul 28 05:14:32 PM PDT 24
Peak memory 196388 kb
Host smart-457599e0-3798-44e1-83c3-adcfd9fc6177
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732323873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3732323873
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2124418698
Short name T704
Test name
Test status
Simulation time 266631025 ps
CPU time 1.08 seconds
Started Jul 28 05:14:32 PM PDT 24
Finished Jul 28 05:14:33 PM PDT 24
Peak memory 196496 kb
Host smart-314cf57e-5b29-4ece-954a-49267027b8ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124418698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2124418698
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.874243719
Short name T640
Test name
Test status
Simulation time 112660800 ps
CPU time 1.18 seconds
Started Jul 28 05:14:29 PM PDT 24
Finished Jul 28 05:14:30 PM PDT 24
Peak memory 197200 kb
Host smart-6efd748b-5e13-4fab-a4f3-f7d543b00e19
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874243719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.gpio_intr_with_filter_rand_intr_event.874243719
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1729477734
Short name T110
Test name
Test status
Simulation time 906487524 ps
CPU time 1.66 seconds
Started Jul 28 05:14:28 PM PDT 24
Finished Jul 28 05:14:30 PM PDT 24
Peak memory 196256 kb
Host smart-2687ef64-a027-4b6e-80ca-522f00f2fff7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729477734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1729477734
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2352378177
Short name T17
Test name
Test status
Simulation time 70326514 ps
CPU time 0.77 seconds
Started Jul 28 05:14:29 PM PDT 24
Finished Jul 28 05:14:30 PM PDT 24
Peak memory 195996 kb
Host smart-b7af43be-d3fd-403d-bf8d-2ab64578e0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352378177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2352378177
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.106466164
Short name T24
Test name
Test status
Simulation time 117954932 ps
CPU time 1.25 seconds
Started Jul 28 05:14:29 PM PDT 24
Finished Jul 28 05:14:30 PM PDT 24
Peak memory 197716 kb
Host smart-85d25744-d198-407a-82b4-6c16f29c58ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106466164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.106466164
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.123097485
Short name T381
Test name
Test status
Simulation time 245621873 ps
CPU time 1.52 seconds
Started Jul 28 05:14:29 PM PDT 24
Finished Jul 28 05:14:31 PM PDT 24
Peak memory 198492 kb
Host smart-61a05794-d74f-4715-84f2-4a7b6b186765
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123097485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ran
dom_long_reg_writes_reg_reads.123097485
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1699489089
Short name T228
Test name
Test status
Simulation time 27701225 ps
CPU time 0.82 seconds
Started Jul 28 05:14:32 PM PDT 24
Finished Jul 28 05:14:33 PM PDT 24
Peak memory 195852 kb
Host smart-2824a499-9225-4d76-ae72-076b5ebfcc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699489089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1699489089
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2957338747
Short name T131
Test name
Test status
Simulation time 33501464 ps
CPU time 0.94 seconds
Started Jul 28 05:14:34 PM PDT 24
Finished Jul 28 05:14:35 PM PDT 24
Peak memory 196260 kb
Host smart-67826edc-41e9-4d46-911c-4d59fff8310a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957338747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2957338747
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1664023348
Short name T386
Test name
Test status
Simulation time 1501762363 ps
CPU time 38.43 seconds
Started Jul 28 05:14:30 PM PDT 24
Finished Jul 28 05:15:08 PM PDT 24
Peak memory 198476 kb
Host smart-4be2e51d-8a90-4a03-b9b1-3fcb1469dae0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664023348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1664023348
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.148827437
Short name T594
Test name
Test status
Simulation time 12498275 ps
CPU time 0.6 seconds
Started Jul 28 05:14:35 PM PDT 24
Finished Jul 28 05:14:36 PM PDT 24
Peak memory 194412 kb
Host smart-59e3660a-b0ed-4236-8737-ea9fa07bc321
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148827437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.148827437
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2527770153
Short name T713
Test name
Test status
Simulation time 48789383 ps
CPU time 0.75 seconds
Started Jul 28 05:14:39 PM PDT 24
Finished Jul 28 05:14:39 PM PDT 24
Peak memory 195716 kb
Host smart-66b7e2d3-d660-4694-bf85-bf5821af77d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527770153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2527770153
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1331801748
Short name T168
Test name
Test status
Simulation time 784290988 ps
CPU time 27.05 seconds
Started Jul 28 05:14:31 PM PDT 24
Finished Jul 28 05:14:58 PM PDT 24
Peak memory 197484 kb
Host smart-9a3902bf-0a9d-48ff-9f2e-df01c2e5e578
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331801748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1331801748
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2249716208
Short name T542
Test name
Test status
Simulation time 120856782 ps
CPU time 0.89 seconds
Started Jul 28 05:14:29 PM PDT 24
Finished Jul 28 05:14:35 PM PDT 24
Peak memory 197224 kb
Host smart-bbcfba52-ddc2-49a5-ae76-9558152f1ebf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249716208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2249716208
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.656864120
Short name T254
Test name
Test status
Simulation time 89665435 ps
CPU time 1.37 seconds
Started Jul 28 05:14:29 PM PDT 24
Finished Jul 28 05:14:30 PM PDT 24
Peak memory 196280 kb
Host smart-024037c6-f135-4ec9-bd78-c0bf3b728a1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656864120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.656864120
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.4095744102
Short name T488
Test name
Test status
Simulation time 81533370 ps
CPU time 3.13 seconds
Started Jul 28 05:14:28 PM PDT 24
Finished Jul 28 05:14:31 PM PDT 24
Peak memory 198676 kb
Host smart-f109ffaa-4364-4a51-83a4-1ebe525e37fb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095744102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.4095744102
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3222716747
Short name T607
Test name
Test status
Simulation time 181817252 ps
CPU time 2.2 seconds
Started Jul 28 05:14:34 PM PDT 24
Finished Jul 28 05:14:37 PM PDT 24
Peak memory 198464 kb
Host smart-daf90985-c7ea-4c6b-8ce2-2a36330a108f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222716747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3222716747
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1409814912
Short name T85
Test name
Test status
Simulation time 59971296 ps
CPU time 1.3 seconds
Started Jul 28 05:14:37 PM PDT 24
Finished Jul 28 05:14:38 PM PDT 24
Peak memory 197520 kb
Host smart-1207f433-d499-4dab-98fd-c21e27cd37a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409814912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1409814912
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.603674990
Short name T650
Test name
Test status
Simulation time 52861583 ps
CPU time 1.02 seconds
Started Jul 28 05:14:29 PM PDT 24
Finished Jul 28 05:14:33 PM PDT 24
Peak memory 196364 kb
Host smart-a5d6e360-4f30-403e-97a7-ee26b7c89440
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603674990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup
_pulldown.603674990
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2498625695
Short name T648
Test name
Test status
Simulation time 86019904 ps
CPU time 4.02 seconds
Started Jul 28 05:14:39 PM PDT 24
Finished Jul 28 05:14:43 PM PDT 24
Peak memory 198436 kb
Host smart-9cbf5191-173b-46a2-beea-63302d61fdd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498625695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2498625695
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.2013420799
Short name T437
Test name
Test status
Simulation time 117189713 ps
CPU time 0.98 seconds
Started Jul 28 05:14:29 PM PDT 24
Finished Jul 28 05:14:30 PM PDT 24
Peak memory 196224 kb
Host smart-7a020836-0e06-426e-b23f-4b8c4b37d9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013420799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.2013420799
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3333588259
Short name T345
Test name
Test status
Simulation time 431309849 ps
CPU time 1.17 seconds
Started Jul 28 05:14:30 PM PDT 24
Finished Jul 28 05:14:31 PM PDT 24
Peak memory 198548 kb
Host smart-d03e4396-d4e0-4a6b-9e54-0a9caa4726d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333588259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3333588259
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3104400648
Short name T490
Test name
Test status
Simulation time 9541800189 ps
CPU time 57.13 seconds
Started Jul 28 05:14:32 PM PDT 24
Finished Jul 28 05:15:29 PM PDT 24
Peak memory 198416 kb
Host smart-bbeb0b0b-4673-4439-96b0-daaabfee9b60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104400648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3104400648
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2374525392
Short name T243
Test name
Test status
Simulation time 17680552 ps
CPU time 0.56 seconds
Started Jul 28 05:14:31 PM PDT 24
Finished Jul 28 05:14:32 PM PDT 24
Peak memory 194400 kb
Host smart-718f9643-1891-4edd-911e-fd9fbd9d7d78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374525392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2374525392
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2592188833
Short name T388
Test name
Test status
Simulation time 26021301 ps
CPU time 0.87 seconds
Started Jul 28 05:14:46 PM PDT 24
Finished Jul 28 05:14:47 PM PDT 24
Peak memory 195680 kb
Host smart-18cb3432-7abd-4bc8-8f50-e82c81817fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592188833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2592188833
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.743140685
Short name T86
Test name
Test status
Simulation time 113953218 ps
CPU time 4.06 seconds
Started Jul 28 05:14:33 PM PDT 24
Finished Jul 28 05:14:37 PM PDT 24
Peak memory 197128 kb
Host smart-c9ad647d-ddca-4cab-b7ef-127fc1720d8a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743140685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stres
s.743140685
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3819700758
Short name T534
Test name
Test status
Simulation time 70322621 ps
CPU time 0.94 seconds
Started Jul 28 05:14:32 PM PDT 24
Finished Jul 28 05:14:33 PM PDT 24
Peak memory 198212 kb
Host smart-0bf84ef4-ed6a-45ef-a829-0136826fd922
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819700758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3819700758
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1387118383
Short name T293
Test name
Test status
Simulation time 184100990 ps
CPU time 0.7 seconds
Started Jul 28 05:14:33 PM PDT 24
Finished Jul 28 05:14:34 PM PDT 24
Peak memory 195552 kb
Host smart-c3b7d043-8175-47f7-9403-12f58a524251
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387118383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1387118383
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1520834896
Short name T253
Test name
Test status
Simulation time 161022369 ps
CPU time 2.99 seconds
Started Jul 28 05:14:28 PM PDT 24
Finished Jul 28 05:14:31 PM PDT 24
Peak memory 198704 kb
Host smart-e430b526-7b15-43ee-be4e-a9546703062b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520834896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1520834896
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.3995128714
Short name T419
Test name
Test status
Simulation time 163181964 ps
CPU time 2.87 seconds
Started Jul 28 05:14:27 PM PDT 24
Finished Jul 28 05:14:30 PM PDT 24
Peak memory 197532 kb
Host smart-41736604-d2d8-4eac-9020-e1dfb75287cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995128714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.3995128714
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.3370203494
Short name T89
Test name
Test status
Simulation time 68060550 ps
CPU time 1.21 seconds
Started Jul 28 05:14:29 PM PDT 24
Finished Jul 28 05:14:30 PM PDT 24
Peak memory 196356 kb
Host smart-d2d1134e-0891-4267-9960-e1eee995a5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370203494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.3370203494
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2420157836
Short name T547
Test name
Test status
Simulation time 109195832 ps
CPU time 0.67 seconds
Started Jul 28 05:14:36 PM PDT 24
Finished Jul 28 05:14:37 PM PDT 24
Peak memory 195724 kb
Host smart-e4aa2f65-1e59-4399-a1cb-cd349115c5ee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420157836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.2420157836
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.4178311686
Short name T84
Test name
Test status
Simulation time 215265362 ps
CPU time 3.64 seconds
Started Jul 28 05:14:35 PM PDT 24
Finished Jul 28 05:14:38 PM PDT 24
Peak memory 198428 kb
Host smart-8929d2de-abd1-45d4-b1cc-7d8cd707d407
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178311686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.4178311686
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.267963473
Short name T600
Test name
Test status
Simulation time 223360897 ps
CPU time 1.28 seconds
Started Jul 28 05:14:39 PM PDT 24
Finished Jul 28 05:14:41 PM PDT 24
Peak memory 197696 kb
Host smart-89f73f4e-b590-4626-9958-e73833ceb90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267963473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.267963473
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.4287626239
Short name T684
Test name
Test status
Simulation time 34483252 ps
CPU time 0.8 seconds
Started Jul 28 05:14:35 PM PDT 24
Finished Jul 28 05:14:35 PM PDT 24
Peak memory 196380 kb
Host smart-27281ebb-4ebe-4490-aabd-c53a3ef4cfd4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287626239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.4287626239
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.1378933899
Short name T121
Test name
Test status
Simulation time 75388056786 ps
CPU time 214.34 seconds
Started Jul 28 05:14:37 PM PDT 24
Finished Jul 28 05:18:12 PM PDT 24
Peak memory 198628 kb
Host smart-f81d20c1-3be3-4acb-8642-fca94022b065
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378933899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.1378933899
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.1372138445
Short name T330
Test name
Test status
Simulation time 24300704955 ps
CPU time 701.92 seconds
Started Jul 28 05:14:27 PM PDT 24
Finished Jul 28 05:26:09 PM PDT 24
Peak memory 198756 kb
Host smart-5ec21265-f020-4fec-a581-19acb2b6adbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1372138445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.1372138445
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3376798962
Short name T183
Test name
Test status
Simulation time 22990987 ps
CPU time 0.58 seconds
Started Jul 28 05:14:55 PM PDT 24
Finished Jul 28 05:14:56 PM PDT 24
Peak memory 194616 kb
Host smart-2021c0fb-738f-446f-9a12-b5998482d515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376798962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3376798962
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2168074566
Short name T480
Test name
Test status
Simulation time 35832735 ps
CPU time 0.85 seconds
Started Jul 28 05:14:36 PM PDT 24
Finished Jul 28 05:14:37 PM PDT 24
Peak memory 196884 kb
Host smart-596d240a-79aa-4bee-9c6d-48a1f9a84bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168074566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2168074566
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1261600178
Short name T582
Test name
Test status
Simulation time 331118519 ps
CPU time 16.04 seconds
Started Jul 28 05:14:46 PM PDT 24
Finished Jul 28 05:15:02 PM PDT 24
Peak memory 197232 kb
Host smart-1bf6f9dc-8607-402d-b11d-1dd1c42d975b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261600178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1261600178
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3245636525
Short name T527
Test name
Test status
Simulation time 29380710 ps
CPU time 0.62 seconds
Started Jul 28 05:14:40 PM PDT 24
Finished Jul 28 05:14:40 PM PDT 24
Peak memory 195792 kb
Host smart-da3cd640-8258-460a-85b8-890750b59c69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245636525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3245636525
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1172316928
Short name T581
Test name
Test status
Simulation time 325710355 ps
CPU time 1.03 seconds
Started Jul 28 05:14:56 PM PDT 24
Finished Jul 28 05:14:57 PM PDT 24
Peak memory 196476 kb
Host smart-ef007dcd-d57c-4e69-930d-5bbe68a5c76d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172316928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1172316928
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.939849676
Short name T523
Test name
Test status
Simulation time 39000653 ps
CPU time 1.59 seconds
Started Jul 28 05:14:43 PM PDT 24
Finished Jul 28 05:14:44 PM PDT 24
Peak memory 197104 kb
Host smart-2797e9cb-a6da-45c1-81d3-7a017b7059d5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939849676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.939849676
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1095334643
Short name T355
Test name
Test status
Simulation time 1372363019 ps
CPU time 2.73 seconds
Started Jul 28 05:14:49 PM PDT 24
Finished Jul 28 05:14:52 PM PDT 24
Peak memory 197432 kb
Host smart-0b8bcc1f-e612-4ea3-8132-007f30d628f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095334643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1095334643
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.2915803107
Short name T413
Test name
Test status
Simulation time 42236698 ps
CPU time 1 seconds
Started Jul 28 05:14:30 PM PDT 24
Finished Jul 28 05:14:31 PM PDT 24
Peak memory 197152 kb
Host smart-7423b1db-430d-4aaf-9070-4a58bd97ae77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915803107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2915803107
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1304304630
Short name T517
Test name
Test status
Simulation time 47734969 ps
CPU time 0.7 seconds
Started Jul 28 05:14:33 PM PDT 24
Finished Jul 28 05:14:34 PM PDT 24
Peak memory 195716 kb
Host smart-58e21f7d-6bdb-45b8-9a02-931f5797a6bc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304304630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1304304630
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.508650177
Short name T706
Test name
Test status
Simulation time 62806271 ps
CPU time 1.32 seconds
Started Jul 28 05:14:38 PM PDT 24
Finished Jul 28 05:14:40 PM PDT 24
Peak memory 198452 kb
Host smart-cb059ca1-7668-47e6-bc5f-6ed8a6679c6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508650177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.508650177
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2669385221
Short name T497
Test name
Test status
Simulation time 36144867 ps
CPU time 0.77 seconds
Started Jul 28 05:14:27 PM PDT 24
Finished Jul 28 05:14:28 PM PDT 24
Peak memory 195592 kb
Host smart-daba53df-e3db-47cc-bd86-2e0d2a8f7fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669385221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2669385221
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.631238796
Short name T612
Test name
Test status
Simulation time 383469286 ps
CPU time 1.41 seconds
Started Jul 28 05:14:30 PM PDT 24
Finished Jul 28 05:14:31 PM PDT 24
Peak memory 197324 kb
Host smart-7cab01a9-cde6-4369-8eee-ca5aefce8102
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631238796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.631238796
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.2550923595
Short name T531
Test name
Test status
Simulation time 187378881505 ps
CPU time 600.64 seconds
Started Jul 28 05:14:52 PM PDT 24
Finished Jul 28 05:24:53 PM PDT 24
Peak memory 198696 kb
Host smart-2d4fff4a-0ddf-4e8f-b5da-366062f87e95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2550923595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.2550923595
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3101630961
Short name T578
Test name
Test status
Simulation time 71775283 ps
CPU time 0.67 seconds
Started Jul 28 05:14:34 PM PDT 24
Finished Jul 28 05:14:34 PM PDT 24
Peak memory 195220 kb
Host smart-09ff122c-54de-4e67-a056-ddc2d0029168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101630961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3101630961
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.1909239098
Short name T456
Test name
Test status
Simulation time 3917961443 ps
CPU time 21.18 seconds
Started Jul 28 05:14:42 PM PDT 24
Finished Jul 28 05:15:03 PM PDT 24
Peak memory 197036 kb
Host smart-d073e66b-dddf-438b-bf42-9df33a7262cd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909239098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.1909239098
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2914554979
Short name T341
Test name
Test status
Simulation time 71584486 ps
CPU time 0.97 seconds
Started Jul 28 05:14:43 PM PDT 24
Finished Jul 28 05:14:45 PM PDT 24
Peak memory 198348 kb
Host smart-d7e66494-eb4a-4ef2-8db6-529b2e95942b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914554979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2914554979
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1855426166
Short name T156
Test name
Test status
Simulation time 93360767 ps
CPU time 1.36 seconds
Started Jul 28 05:14:54 PM PDT 24
Finished Jul 28 05:14:55 PM PDT 24
Peak memory 197540 kb
Host smart-f8525445-e394-4365-b32d-b7276980ace4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855426166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1855426166
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3374323267
Short name T258
Test name
Test status
Simulation time 47268256 ps
CPU time 1.15 seconds
Started Jul 28 05:14:50 PM PDT 24
Finished Jul 28 05:14:52 PM PDT 24
Peak memory 197280 kb
Host smart-7f70ee59-26f9-4ae7-a18d-4658f20c1cc0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374323267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3374323267
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.716303142
Short name T657
Test name
Test status
Simulation time 243167483 ps
CPU time 3.46 seconds
Started Jul 28 05:14:36 PM PDT 24
Finished Jul 28 05:14:39 PM PDT 24
Peak memory 197576 kb
Host smart-ce5633b0-6f14-420a-a0ef-465ca2529070
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716303142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
716303142
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.841649167
Short name T221
Test name
Test status
Simulation time 70122532 ps
CPU time 0.83 seconds
Started Jul 28 05:14:34 PM PDT 24
Finished Jul 28 05:14:35 PM PDT 24
Peak memory 197000 kb
Host smart-fa6a55ba-30e6-47be-9933-35e803ba916b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841649167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.841649167
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1478486174
Short name T307
Test name
Test status
Simulation time 18051184 ps
CPU time 0.7 seconds
Started Jul 28 05:14:43 PM PDT 24
Finished Jul 28 05:14:44 PM PDT 24
Peak memory 194932 kb
Host smart-10c214a2-1995-45c6-a6da-03bcc9a84f86
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478486174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1478486174
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.33661429
Short name T540
Test name
Test status
Simulation time 1408921504 ps
CPU time 6.01 seconds
Started Jul 28 05:14:42 PM PDT 24
Finished Jul 28 05:14:48 PM PDT 24
Peak memory 198476 kb
Host smart-0c98cc9c-4170-40a2-955d-731cf0b51cb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33661429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand
om_long_reg_writes_reg_reads.33661429
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.1136517168
Short name T166
Test name
Test status
Simulation time 224978711 ps
CPU time 1.16 seconds
Started Jul 28 05:14:50 PM PDT 24
Finished Jul 28 05:14:51 PM PDT 24
Peak memory 196248 kb
Host smart-f740772e-cdcf-42c9-a999-62ae99ad4d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136517168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.1136517168
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1037574942
Short name T389
Test name
Test status
Simulation time 32983604 ps
CPU time 0.78 seconds
Started Jul 28 05:14:32 PM PDT 24
Finished Jul 28 05:14:38 PM PDT 24
Peak memory 196276 kb
Host smart-7491a642-f291-4932-95f9-0e35daa3ec89
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037574942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1037574942
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1724304079
Short name T22
Test name
Test status
Simulation time 68108808277 ps
CPU time 96.47 seconds
Started Jul 28 05:14:34 PM PDT 24
Finished Jul 28 05:16:11 PM PDT 24
Peak memory 198576 kb
Host smart-a7bc4f17-3e72-4f77-9799-eef87a76aefe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724304079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1724304079
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3839446480
Short name T157
Test name
Test status
Simulation time 18336741 ps
CPU time 0.59 seconds
Started Jul 28 05:14:48 PM PDT 24
Finished Jul 28 05:14:49 PM PDT 24
Peak memory 194692 kb
Host smart-bbb41c68-2100-4c10-82c1-a1fa8ff61766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839446480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3839446480
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3356778391
Short name T700
Test name
Test status
Simulation time 33733034 ps
CPU time 0.59 seconds
Started Jul 28 05:14:57 PM PDT 24
Finished Jul 28 05:14:57 PM PDT 24
Peak memory 195160 kb
Host smart-45addf37-8033-4499-97e7-a841b43313b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356778391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3356778391
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.4287056776
Short name T658
Test name
Test status
Simulation time 1592884596 ps
CPU time 14.07 seconds
Started Jul 28 05:14:50 PM PDT 24
Finished Jul 28 05:15:04 PM PDT 24
Peak memory 196024 kb
Host smart-cf821062-ccd6-404c-bc7c-c982de1ce9a4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287056776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.4287056776
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3266654017
Short name T9
Test name
Test status
Simulation time 297838595 ps
CPU time 0.94 seconds
Started Jul 28 05:14:50 PM PDT 24
Finished Jul 28 05:14:51 PM PDT 24
Peak memory 197592 kb
Host smart-5440b4a7-7f51-4bc3-98ec-6de839d07056
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266654017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3266654017
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1012437320
Short name T194
Test name
Test status
Simulation time 97909014 ps
CPU time 1.3 seconds
Started Jul 28 05:14:42 PM PDT 24
Finished Jul 28 05:14:43 PM PDT 24
Peak memory 197552 kb
Host smart-780dce20-bf5e-44a3-8dc7-78facb149d1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012437320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1012437320
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1729599107
Short name T696
Test name
Test status
Simulation time 89284037 ps
CPU time 1.86 seconds
Started Jul 28 05:14:39 PM PDT 24
Finished Jul 28 05:14:41 PM PDT 24
Peak memory 198616 kb
Host smart-2a6475e4-e8cb-4548-9d15-eeadaae77f40
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729599107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1729599107
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3039703303
Short name T409
Test name
Test status
Simulation time 596003632 ps
CPU time 3.18 seconds
Started Jul 28 05:14:32 PM PDT 24
Finished Jul 28 05:14:35 PM PDT 24
Peak memory 197624 kb
Host smart-e560240b-2fe6-43ac-82f7-73a5970db5a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039703303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3039703303
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3797516519
Short name T185
Test name
Test status
Simulation time 210927960 ps
CPU time 0.7 seconds
Started Jul 28 05:14:32 PM PDT 24
Finished Jul 28 05:14:33 PM PDT 24
Peak memory 195804 kb
Host smart-6dcc2abb-6ca0-4a4d-94bc-7a1fc89a2123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797516519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3797516519
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.4164665019
Short name T18
Test name
Test status
Simulation time 52017616 ps
CPU time 0.97 seconds
Started Jul 28 05:14:55 PM PDT 24
Finished Jul 28 05:14:56 PM PDT 24
Peak memory 196492 kb
Host smart-8314dbdd-f6a9-4c19-9f99-e6de8b64a873
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164665019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.4164665019
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1797736396
Short name T591
Test name
Test status
Simulation time 658448380 ps
CPU time 5.2 seconds
Started Jul 28 05:14:35 PM PDT 24
Finished Jul 28 05:14:40 PM PDT 24
Peak memory 198480 kb
Host smart-eb56aa47-139c-4a13-83d1-7b21346f8129
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797736396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1797736396
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.3766352164
Short name T288
Test name
Test status
Simulation time 37072198 ps
CPU time 0.84 seconds
Started Jul 28 05:14:42 PM PDT 24
Finished Jul 28 05:14:43 PM PDT 24
Peak memory 197380 kb
Host smart-18bdaca0-ae6e-41be-920a-4d234814a53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766352164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.3766352164
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.553467274
Short name T666
Test name
Test status
Simulation time 80950753 ps
CPU time 1.27 seconds
Started Jul 28 05:14:54 PM PDT 24
Finished Jul 28 05:14:56 PM PDT 24
Peak memory 198428 kb
Host smart-99ec275d-4bdc-4ec5-bd6c-e4ffd72c24d2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553467274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.553467274
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.4232311586
Short name T180
Test name
Test status
Simulation time 13018906758 ps
CPU time 85.31 seconds
Started Jul 28 05:14:41 PM PDT 24
Finished Jul 28 05:16:07 PM PDT 24
Peak memory 198576 kb
Host smart-fcb7e99e-098d-4900-8fcc-da69c0a3e90d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232311586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.4232311586
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.623573352
Short name T514
Test name
Test status
Simulation time 48376139 ps
CPU time 0.55 seconds
Started Jul 28 05:15:08 PM PDT 24
Finished Jul 28 05:15:08 PM PDT 24
Peak memory 194428 kb
Host smart-977a1ab8-4c27-4f7f-818c-644b7ea8876f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623573352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.623573352
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.690139435
Short name T515
Test name
Test status
Simulation time 84317493 ps
CPU time 0.93 seconds
Started Jul 28 05:14:47 PM PDT 24
Finished Jul 28 05:14:48 PM PDT 24
Peak memory 196992 kb
Host smart-6e6ba513-1de9-4774-b232-26a21936e356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690139435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.690139435
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2734631802
Short name T430
Test name
Test status
Simulation time 1008911464 ps
CPU time 17.56 seconds
Started Jul 28 05:14:50 PM PDT 24
Finished Jul 28 05:15:08 PM PDT 24
Peak memory 197456 kb
Host smart-18fea5da-7e9b-45a3-a04b-e440861b4332
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734631802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2734631802
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2550721475
Short name T19
Test name
Test status
Simulation time 36291220 ps
CPU time 0.7 seconds
Started Jul 28 05:14:54 PM PDT 24
Finished Jul 28 05:14:55 PM PDT 24
Peak memory 195248 kb
Host smart-b945e590-85e8-4448-ad23-4c1a52d8483c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550721475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2550721475
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3135745409
Short name T316
Test name
Test status
Simulation time 192845813 ps
CPU time 1.42 seconds
Started Jul 28 05:14:55 PM PDT 24
Finished Jul 28 05:14:57 PM PDT 24
Peak memory 198528 kb
Host smart-570121c6-9f85-4b0c-8d48-17cba2231b33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135745409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3135745409
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.131147844
Short name T308
Test name
Test status
Simulation time 45352210 ps
CPU time 1.88 seconds
Started Jul 28 05:14:52 PM PDT 24
Finished Jul 28 05:14:54 PM PDT 24
Peak memory 198568 kb
Host smart-b839e875-4e6d-46e4-8c98-12b5d8bd627c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131147844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.131147844
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2994529516
Short name T718
Test name
Test status
Simulation time 915472553 ps
CPU time 3.53 seconds
Started Jul 28 05:14:43 PM PDT 24
Finished Jul 28 05:14:46 PM PDT 24
Peak memory 196312 kb
Host smart-829e3cba-28c9-4105-9152-5899838b9ceb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994529516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2994529516
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3632402824
Short name T525
Test name
Test status
Simulation time 36892559 ps
CPU time 0.83 seconds
Started Jul 28 05:14:52 PM PDT 24
Finished Jul 28 05:14:53 PM PDT 24
Peak memory 196856 kb
Host smart-b03f28e5-817c-4ba2-ba22-794875e3ade4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632402824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3632402824
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1909049253
Short name T281
Test name
Test status
Simulation time 95432320 ps
CPU time 0.66 seconds
Started Jul 28 05:14:45 PM PDT 24
Finished Jul 28 05:14:46 PM PDT 24
Peak memory 194752 kb
Host smart-ef6e0df1-6d5d-4142-959f-75ad80e4b39c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909049253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1909049253
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3436143422
Short name T361
Test name
Test status
Simulation time 83131927 ps
CPU time 1.77 seconds
Started Jul 28 05:14:50 PM PDT 24
Finished Jul 28 05:14:52 PM PDT 24
Peak memory 198452 kb
Host smart-09507e59-1adf-4499-8eea-07dfcad87569
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436143422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3436143422
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.33064848
Short name T104
Test name
Test status
Simulation time 182513483 ps
CPU time 0.96 seconds
Started Jul 28 05:14:50 PM PDT 24
Finished Jul 28 05:14:51 PM PDT 24
Peak memory 196260 kb
Host smart-dd65870d-a9a3-4f30-ab29-0856c89d7ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33064848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.33064848
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.2534322608
Short name T462
Test name
Test status
Simulation time 372889587 ps
CPU time 1.39 seconds
Started Jul 28 05:14:43 PM PDT 24
Finished Jul 28 05:14:50 PM PDT 24
Peak memory 196152 kb
Host smart-b8ab3b81-93f4-4850-b341-8fb5982c8f42
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534322608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.2534322608
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3975091090
Short name T2
Test name
Test status
Simulation time 16489152766 ps
CPU time 83.22 seconds
Started Jul 28 05:15:08 PM PDT 24
Finished Jul 28 05:16:31 PM PDT 24
Peak memory 198636 kb
Host smart-87ff0ace-325c-4a72-82b7-fbb0c3af57eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975091090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3975091090
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.3545874245
Short name T93
Test name
Test status
Simulation time 70006986999 ps
CPU time 857.83 seconds
Started Jul 28 05:14:54 PM PDT 24
Finished Jul 28 05:29:12 PM PDT 24
Peak memory 198796 kb
Host smart-be35183e-e12d-4cff-836c-d2f6fad13089
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3545874245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.3545874245
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2830353974
Short name T549
Test name
Test status
Simulation time 19095644 ps
CPU time 0.55 seconds
Started Jul 28 05:14:53 PM PDT 24
Finished Jul 28 05:14:54 PM PDT 24
Peak memory 194408 kb
Host smart-fed97478-c2ed-4501-9ec2-927f29bd5e47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830353974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2830353974
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.582088497
Short name T126
Test name
Test status
Simulation time 264467359 ps
CPU time 0.88 seconds
Started Jul 28 05:14:50 PM PDT 24
Finished Jul 28 05:14:51 PM PDT 24
Peak memory 196812 kb
Host smart-baa69178-424c-4647-84e1-bad5c13d91c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582088497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.582088497
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1915420235
Short name T160
Test name
Test status
Simulation time 219885095 ps
CPU time 11.37 seconds
Started Jul 28 05:14:53 PM PDT 24
Finished Jul 28 05:15:05 PM PDT 24
Peak memory 196044 kb
Host smart-d479599a-73cd-4f60-af7c-a3d7f28c8b07
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915420235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1915420235
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2072748181
Short name T23
Test name
Test status
Simulation time 137556254 ps
CPU time 0.94 seconds
Started Jul 28 05:14:57 PM PDT 24
Finished Jul 28 05:14:58 PM PDT 24
Peak memory 197200 kb
Host smart-ebfd9fd3-6977-46dc-b1b5-818483baef54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072748181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2072748181
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2546260888
Short name T553
Test name
Test status
Simulation time 65489566 ps
CPU time 1.21 seconds
Started Jul 28 05:15:06 PM PDT 24
Finished Jul 28 05:15:07 PM PDT 24
Peak memory 197136 kb
Host smart-3896e5f2-b6dc-4e17-80de-c7c0b3fba5d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546260888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2546260888
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3486848510
Short name T215
Test name
Test status
Simulation time 242925054 ps
CPU time 2.5 seconds
Started Jul 28 05:14:56 PM PDT 24
Finished Jul 28 05:14:58 PM PDT 24
Peak memory 198756 kb
Host smart-105da8d8-02e5-4cd4-a7e8-9ed744c93dab
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486848510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3486848510
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.477936500
Short name T378
Test name
Test status
Simulation time 435483670 ps
CPU time 2.05 seconds
Started Jul 28 05:14:38 PM PDT 24
Finished Jul 28 05:14:40 PM PDT 24
Peak memory 196988 kb
Host smart-a030af9e-5a90-4514-9485-9e3717388d6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477936500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
477936500
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.2991982640
Short name T478
Test name
Test status
Simulation time 64746163 ps
CPU time 0.74 seconds
Started Jul 28 05:14:57 PM PDT 24
Finished Jul 28 05:14:58 PM PDT 24
Peak memory 195796 kb
Host smart-1b0ca2af-c481-4bb7-bf89-97f851418d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991982640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2991982640
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3546178989
Short name T16
Test name
Test status
Simulation time 782597938 ps
CPU time 1.26 seconds
Started Jul 28 05:14:50 PM PDT 24
Finished Jul 28 05:14:51 PM PDT 24
Peak memory 198504 kb
Host smart-3d32308b-647f-41ac-b7e7-15e9bef2c947
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546178989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3546178989
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.4063910410
Short name T135
Test name
Test status
Simulation time 1457202368 ps
CPU time 5.26 seconds
Started Jul 28 05:14:47 PM PDT 24
Finished Jul 28 05:14:53 PM PDT 24
Peak memory 198424 kb
Host smart-61967b50-ea04-4c71-a15c-b98de84ff565
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063910410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.4063910410
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.111369983
Short name T615
Test name
Test status
Simulation time 44230968 ps
CPU time 1.27 seconds
Started Jul 28 05:15:02 PM PDT 24
Finished Jul 28 05:15:03 PM PDT 24
Peak memory 197068 kb
Host smart-ad45001e-1cb5-43f0-b6de-5d292ff383ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111369983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.111369983
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2785533435
Short name T356
Test name
Test status
Simulation time 78564644 ps
CPU time 1.09 seconds
Started Jul 28 05:14:59 PM PDT 24
Finished Jul 28 05:15:00 PM PDT 24
Peak memory 196980 kb
Host smart-e621fd3e-fccc-4414-9f25-eceab0ad9591
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785533435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2785533435
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.1242416556
Short name T21
Test name
Test status
Simulation time 19658042471 ps
CPU time 204.61 seconds
Started Jul 28 05:14:54 PM PDT 24
Finished Jul 28 05:18:19 PM PDT 24
Peak memory 198588 kb
Host smart-3964b44d-413e-4765-bf90-ca1249fd8c11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242416556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.1242416556
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2096878155
Short name T366
Test name
Test status
Simulation time 12472571 ps
CPU time 0.58 seconds
Started Jul 28 05:13:39 PM PDT 24
Finished Jul 28 05:13:40 PM PDT 24
Peak memory 195256 kb
Host smart-ef23a2f5-b547-486a-84a2-bee706624f93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096878155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2096878155
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.900169072
Short name T563
Test name
Test status
Simulation time 49078082 ps
CPU time 0.71 seconds
Started Jul 28 05:13:48 PM PDT 24
Finished Jul 28 05:13:49 PM PDT 24
Peak memory 195680 kb
Host smart-5afe61ca-cfb8-4124-8532-673e2af47aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900169072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.900169072
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1677879701
Short name T716
Test name
Test status
Simulation time 423542265 ps
CPU time 10.82 seconds
Started Jul 28 05:14:04 PM PDT 24
Finished Jul 28 05:14:15 PM PDT 24
Peak memory 197356 kb
Host smart-8c22d644-2062-4209-8056-801e35125140
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677879701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1677879701
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.216275952
Short name T240
Test name
Test status
Simulation time 23408635 ps
CPU time 0.65 seconds
Started Jul 28 05:13:37 PM PDT 24
Finished Jul 28 05:13:38 PM PDT 24
Peak memory 195172 kb
Host smart-d3fb1181-6631-4199-a1fd-9246a7fb02ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216275952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.216275952
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2946316661
Short name T337
Test name
Test status
Simulation time 49040998 ps
CPU time 0.71 seconds
Started Jul 28 05:13:53 PM PDT 24
Finished Jul 28 05:13:54 PM PDT 24
Peak memory 195484 kb
Host smart-b898cf20-6e68-4ed4-a0da-49df2c1c1844
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946316661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2946316661
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1523093606
Short name T334
Test name
Test status
Simulation time 54135053 ps
CPU time 2.02 seconds
Started Jul 28 05:13:36 PM PDT 24
Finished Jul 28 05:13:38 PM PDT 24
Peak memory 198644 kb
Host smart-9e9863dc-872b-415f-ac62-57da6dc31b93
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523093606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1523093606
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2621987839
Short name T364
Test name
Test status
Simulation time 183515401 ps
CPU time 2.01 seconds
Started Jul 28 05:13:32 PM PDT 24
Finished Jul 28 05:13:35 PM PDT 24
Peak memory 197160 kb
Host smart-ab17344b-a061-4f9d-bd15-f1081c3b8293
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621987839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2621987839
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.1613476612
Short name T673
Test name
Test status
Simulation time 54162196 ps
CPU time 1.04 seconds
Started Jul 28 05:13:45 PM PDT 24
Finished Jul 28 05:13:46 PM PDT 24
Peak memory 196492 kb
Host smart-e036bff3-d1dc-4965-9d1b-fb27fcfb727b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613476612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1613476612
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2543932871
Short name T190
Test name
Test status
Simulation time 98512450 ps
CPU time 0.78 seconds
Started Jul 28 05:13:45 PM PDT 24
Finished Jul 28 05:13:46 PM PDT 24
Peak memory 196556 kb
Host smart-8050e557-4db7-45c3-9503-68bb3cafdc16
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543932871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2543932871
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2320692448
Short name T384
Test name
Test status
Simulation time 166153721 ps
CPU time 4.66 seconds
Started Jul 28 05:13:44 PM PDT 24
Finished Jul 28 05:13:49 PM PDT 24
Peak memory 198360 kb
Host smart-e3ff04a8-42a8-4e98-91ac-720e58710e20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320692448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2320692448
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.1925668556
Short name T46
Test name
Test status
Simulation time 113895468 ps
CPU time 0.87 seconds
Started Jul 28 05:13:41 PM PDT 24
Finished Jul 28 05:13:42 PM PDT 24
Peak memory 214404 kb
Host smart-cd3c3364-9566-4030-8d6e-5644c96235db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925668556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.1925668556
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.4169386662
Short name T188
Test name
Test status
Simulation time 34926669 ps
CPU time 0.9 seconds
Started Jul 28 05:13:46 PM PDT 24
Finished Jul 28 05:13:47 PM PDT 24
Peak memory 196904 kb
Host smart-60b18e96-bcc9-4672-8e95-5f967aec96f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169386662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.4169386662
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2796070304
Short name T420
Test name
Test status
Simulation time 448596702 ps
CPU time 1.46 seconds
Started Jul 28 05:13:48 PM PDT 24
Finished Jul 28 05:13:50 PM PDT 24
Peak memory 197356 kb
Host smart-d1e50e65-8907-45bd-a549-2bf99b153265
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796070304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2796070304
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.58069655
Short name T711
Test name
Test status
Simulation time 74553735307 ps
CPU time 190.27 seconds
Started Jul 28 05:13:58 PM PDT 24
Finished Jul 28 05:17:09 PM PDT 24
Peak memory 198640 kb
Host smart-e2053a7b-ed4f-42b8-a76c-0127d7aadc4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58069655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpi
o_stress_all.58069655
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.1721304373
Short name T595
Test name
Test status
Simulation time 25928505 ps
CPU time 0.58 seconds
Started Jul 28 05:14:56 PM PDT 24
Finished Jul 28 05:14:57 PM PDT 24
Peak memory 194412 kb
Host smart-60f4dcae-54e5-427d-9975-9fee41ead2ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721304373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.1721304373
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3311173562
Short name T278
Test name
Test status
Simulation time 117623159 ps
CPU time 0.88 seconds
Started Jul 28 05:14:44 PM PDT 24
Finished Jul 28 05:14:45 PM PDT 24
Peak memory 196964 kb
Host smart-328bcc61-a5bc-4c3c-b173-27f99ab8c375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311173562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3311173562
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.978395814
Short name T88
Test name
Test status
Simulation time 1615054285 ps
CPU time 11.79 seconds
Started Jul 28 05:14:58 PM PDT 24
Finished Jul 28 05:15:10 PM PDT 24
Peak memory 198496 kb
Host smart-b0dab6af-6848-4dbf-b7b6-dd7917412b0e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978395814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.978395814
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.417422311
Short name T670
Test name
Test status
Simulation time 125879748 ps
CPU time 0.74 seconds
Started Jul 28 05:14:59 PM PDT 24
Finished Jul 28 05:15:00 PM PDT 24
Peak memory 196196 kb
Host smart-d7b64682-3414-4327-aee9-69e98c848477
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417422311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.417422311
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.551818296
Short name T322
Test name
Test status
Simulation time 66453114 ps
CPU time 1.16 seconds
Started Jul 28 05:14:49 PM PDT 24
Finished Jul 28 05:14:51 PM PDT 24
Peak memory 196628 kb
Host smart-c7111e7c-deb1-471f-9c8c-aeba882c2355
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551818296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.551818296
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.1125083661
Short name T95
Test name
Test status
Simulation time 62925599 ps
CPU time 1.8 seconds
Started Jul 28 05:14:49 PM PDT 24
Finished Jul 28 05:14:51 PM PDT 24
Peak memory 198628 kb
Host smart-8a74532c-ca47-4d63-88f8-9d97ff46f913
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125083661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.1125083661
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.98417403
Short name T328
Test name
Test status
Simulation time 64703587 ps
CPU time 0.86 seconds
Started Jul 28 05:14:50 PM PDT 24
Finished Jul 28 05:14:51 PM PDT 24
Peak memory 195772 kb
Host smart-21ab660a-4ff1-4b93-85fa-181dd22a249f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98417403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.98417403
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.129395205
Short name T87
Test name
Test status
Simulation time 63984294 ps
CPU time 1.11 seconds
Started Jul 28 05:14:54 PM PDT 24
Finished Jul 28 05:14:55 PM PDT 24
Peak memory 197040 kb
Host smart-16fef0c4-b8c1-4f3c-b5e3-f350641833ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129395205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.129395205
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.749157100
Short name T446
Test name
Test status
Simulation time 227195059 ps
CPU time 0.91 seconds
Started Jul 28 05:14:39 PM PDT 24
Finished Jul 28 05:14:40 PM PDT 24
Peak memory 196540 kb
Host smart-80152159-84e4-46c2-b6ef-c021f844c790
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749157100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup
_pulldown.749157100
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.436204466
Short name T146
Test name
Test status
Simulation time 172138573 ps
CPU time 3.92 seconds
Started Jul 28 05:14:44 PM PDT 24
Finished Jul 28 05:14:48 PM PDT 24
Peak memory 198496 kb
Host smart-9fe9ec35-33dd-4575-9c92-cad33b6d026a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436204466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ran
dom_long_reg_writes_reg_reads.436204466
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.723271807
Short name T467
Test name
Test status
Simulation time 17335983 ps
CPU time 0.68 seconds
Started Jul 28 05:14:54 PM PDT 24
Finished Jul 28 05:14:55 PM PDT 24
Peak memory 196320 kb
Host smart-abd8ed97-2ec7-4e90-b174-89298f126c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723271807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.723271807
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2873315701
Short name T241
Test name
Test status
Simulation time 75642129 ps
CPU time 0.88 seconds
Started Jul 28 05:14:43 PM PDT 24
Finished Jul 28 05:14:45 PM PDT 24
Peak memory 196844 kb
Host smart-de6c8e21-da4f-406e-a617-896f2b3cc6f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873315701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2873315701
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3127629075
Short name T133
Test name
Test status
Simulation time 1632368978 ps
CPU time 38.81 seconds
Started Jul 28 05:15:02 PM PDT 24
Finished Jul 28 05:15:41 PM PDT 24
Peak memory 198488 kb
Host smart-0e0c0989-6380-40e6-8389-d5e7225c9706
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127629075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3127629075
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.1973200604
Short name T575
Test name
Test status
Simulation time 42326570911 ps
CPU time 938.11 seconds
Started Jul 28 05:14:55 PM PDT 24
Finished Jul 28 05:30:34 PM PDT 24
Peak memory 198776 kb
Host smart-f60ba263-e24d-46e9-96f4-aef1f15c648b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1973200604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.1973200604
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3590915826
Short name T617
Test name
Test status
Simulation time 20883486 ps
CPU time 0.55 seconds
Started Jul 28 05:14:53 PM PDT 24
Finished Jul 28 05:14:53 PM PDT 24
Peak memory 193892 kb
Host smart-1b00c24d-28e6-447f-bd06-db65d2869c1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590915826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3590915826
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2788978088
Short name T526
Test name
Test status
Simulation time 93322759 ps
CPU time 0.8 seconds
Started Jul 28 05:14:52 PM PDT 24
Finished Jul 28 05:14:53 PM PDT 24
Peak memory 195732 kb
Host smart-78d433f0-e1b0-48eb-811a-4dcce047ee09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788978088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2788978088
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3953919201
Short name T295
Test name
Test status
Simulation time 1345421713 ps
CPU time 6.61 seconds
Started Jul 28 05:14:56 PM PDT 24
Finished Jul 28 05:15:02 PM PDT 24
Peak memory 197416 kb
Host smart-b50e0594-4c48-4ba6-b3c3-377fa13e30ca
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953919201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3953919201
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.3869545482
Short name T458
Test name
Test status
Simulation time 59710557 ps
CPU time 0.74 seconds
Started Jul 28 05:14:45 PM PDT 24
Finished Jul 28 05:14:46 PM PDT 24
Peak memory 196232 kb
Host smart-fae2e165-06e4-43bb-a093-05829d83e841
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869545482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.3869545482
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2700816597
Short name T207
Test name
Test status
Simulation time 30843352 ps
CPU time 0.68 seconds
Started Jul 28 05:14:50 PM PDT 24
Finished Jul 28 05:14:51 PM PDT 24
Peak memory 194728 kb
Host smart-a569beae-c4c2-44c1-b43b-07f09f778844
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700816597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2700816597
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2913659842
Short name T279
Test name
Test status
Simulation time 50441569 ps
CPU time 1.97 seconds
Started Jul 28 05:14:54 PM PDT 24
Finished Jul 28 05:14:57 PM PDT 24
Peak memory 196992 kb
Host smart-56ef9e47-573b-4834-a9ad-d642cd69e561
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913659842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.2913659842
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.813257403
Short name T551
Test name
Test status
Simulation time 116054913 ps
CPU time 1.84 seconds
Started Jul 28 05:14:56 PM PDT 24
Finished Jul 28 05:14:58 PM PDT 24
Peak memory 197732 kb
Host smart-8ca640e1-9e45-4553-9a70-1f7dbe2eb3c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813257403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
813257403
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.1151092766
Short name T136
Test name
Test status
Simulation time 77545575 ps
CPU time 0.82 seconds
Started Jul 28 05:14:57 PM PDT 24
Finished Jul 28 05:14:58 PM PDT 24
Peak memory 195996 kb
Host smart-ebe7245b-7c9a-459b-b6c4-ae2e523f1170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151092766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1151092766
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3069517711
Short name T682
Test name
Test status
Simulation time 42276014 ps
CPU time 1.05 seconds
Started Jul 28 05:14:52 PM PDT 24
Finished Jul 28 05:14:53 PM PDT 24
Peak memory 196476 kb
Host smart-7f15e515-ca20-4de9-b2e7-322b2d37a793
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069517711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3069517711
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2257610367
Short name T702
Test name
Test status
Simulation time 135064774 ps
CPU time 2.41 seconds
Started Jul 28 05:14:53 PM PDT 24
Finished Jul 28 05:14:56 PM PDT 24
Peak memory 198264 kb
Host smart-050d1b39-d5a9-4a32-a2ab-b8aae591365a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257610367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2257610367
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3633585974
Short name T300
Test name
Test status
Simulation time 62155964 ps
CPU time 0.96 seconds
Started Jul 28 05:14:45 PM PDT 24
Finished Jul 28 05:14:46 PM PDT 24
Peak memory 197400 kb
Host smart-a2e5a243-faff-43fa-86f3-30f37b95e4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633585974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3633585974
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3326685488
Short name T262
Test name
Test status
Simulation time 62763310 ps
CPU time 1.01 seconds
Started Jul 28 05:14:50 PM PDT 24
Finished Jul 28 05:14:52 PM PDT 24
Peak memory 196304 kb
Host smart-12c78dc8-4d8c-424f-8046-073846b03c91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326685488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3326685488
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.383449345
Short name T489
Test name
Test status
Simulation time 6390426961 ps
CPU time 73.41 seconds
Started Jul 28 05:14:45 PM PDT 24
Finished Jul 28 05:15:58 PM PDT 24
Peak memory 198572 kb
Host smart-9c8cfc76-0f53-4a83-b964-e2c4e47d207b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383449345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g
pio_stress_all.383449345
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3174109760
Short name T236
Test name
Test status
Simulation time 61196199 ps
CPU time 0.61 seconds
Started Jul 28 05:14:56 PM PDT 24
Finished Jul 28 05:14:57 PM PDT 24
Peak memory 194564 kb
Host smart-8b9edd00-9cc9-405d-8dfc-b269212e663d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174109760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3174109760
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.114885871
Short name T323
Test name
Test status
Simulation time 25192349 ps
CPU time 0.59 seconds
Started Jul 28 05:14:58 PM PDT 24
Finished Jul 28 05:14:59 PM PDT 24
Peak memory 194940 kb
Host smart-72221f6c-b587-4647-b0bd-1bbc5540eaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114885871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.114885871
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.4285168864
Short name T301
Test name
Test status
Simulation time 1206858468 ps
CPU time 7.4 seconds
Started Jul 28 05:15:04 PM PDT 24
Finished Jul 28 05:15:12 PM PDT 24
Peak memory 198324 kb
Host smart-9c0cdadb-f264-47e6-bc41-cdabb74c6495
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285168864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.4285168864
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3854195719
Short name T652
Test name
Test status
Simulation time 166821291 ps
CPU time 0.8 seconds
Started Jul 28 05:14:59 PM PDT 24
Finished Jul 28 05:14:59 PM PDT 24
Peak memory 196476 kb
Host smart-06851ec9-588a-4ffb-88a5-3efea2e34d95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854195719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3854195719
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2729861952
Short name T449
Test name
Test status
Simulation time 142706697 ps
CPU time 1.2 seconds
Started Jul 28 05:14:53 PM PDT 24
Finished Jul 28 05:14:54 PM PDT 24
Peak memory 196700 kb
Host smart-1e644564-221a-481b-b2ed-4856faebd1e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729861952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2729861952
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3309991970
Short name T468
Test name
Test status
Simulation time 198433678 ps
CPU time 2.33 seconds
Started Jul 28 05:14:56 PM PDT 24
Finished Jul 28 05:14:59 PM PDT 24
Peak memory 197736 kb
Host smart-a56ea48e-08bd-47d0-85ce-a2296b09ff1e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309991970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3309991970
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2413255203
Short name T397
Test name
Test status
Simulation time 317016460 ps
CPU time 1.26 seconds
Started Jul 28 05:15:11 PM PDT 24
Finished Jul 28 05:15:12 PM PDT 24
Peak memory 197240 kb
Host smart-76b77de8-ade5-481d-91f9-f210ca028165
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413255203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2413255203
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.1446546103
Short name T631
Test name
Test status
Simulation time 67484535 ps
CPU time 0.92 seconds
Started Jul 28 05:14:56 PM PDT 24
Finished Jul 28 05:14:57 PM PDT 24
Peak memory 196436 kb
Host smart-2b1de8e9-15ce-403a-b89f-1710cd08c0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446546103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1446546103
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3375923264
Short name T629
Test name
Test status
Simulation time 117371926 ps
CPU time 1.2 seconds
Started Jul 28 05:14:50 PM PDT 24
Finished Jul 28 05:14:51 PM PDT 24
Peak memory 198468 kb
Host smart-81a438e4-4158-43c5-bb62-60cc91e7e560
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375923264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3375923264
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.984709201
Short name T590
Test name
Test status
Simulation time 147294407 ps
CPU time 2.52 seconds
Started Jul 28 05:15:03 PM PDT 24
Finished Jul 28 05:15:06 PM PDT 24
Peak memory 198696 kb
Host smart-f25c7ba4-d197-4335-81b4-ae783e1d4ddc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984709201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran
dom_long_reg_writes_reg_reads.984709201
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3674567926
Short name T129
Test name
Test status
Simulation time 38859158 ps
CPU time 0.82 seconds
Started Jul 28 05:14:54 PM PDT 24
Finished Jul 28 05:14:55 PM PDT 24
Peak memory 195636 kb
Host smart-0b00e116-03a3-408f-b98c-32db7539d182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674567926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3674567926
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2637863611
Short name T137
Test name
Test status
Simulation time 313165642 ps
CPU time 1.26 seconds
Started Jul 28 05:14:55 PM PDT 24
Finished Jul 28 05:14:56 PM PDT 24
Peak memory 196288 kb
Host smart-e5bc0242-2b3a-445c-82f0-5f92b6abd9f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637863611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2637863611
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.2821824134
Short name T289
Test name
Test status
Simulation time 7240260587 ps
CPU time 94.54 seconds
Started Jul 28 05:15:06 PM PDT 24
Finished Jul 28 05:16:41 PM PDT 24
Peak memory 198516 kb
Host smart-d318fbac-8c5d-4dcd-b790-81efcc9aa3f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821824134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.2821824134
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1996504904
Short name T667
Test name
Test status
Simulation time 128012747 ps
CPU time 0.54 seconds
Started Jul 28 05:15:11 PM PDT 24
Finished Jul 28 05:15:12 PM PDT 24
Peak memory 194452 kb
Host smart-cc2c6125-2fdb-439f-b747-4839ecaca5cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996504904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1996504904
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.325663101
Short name T679
Test name
Test status
Simulation time 173643142 ps
CPU time 0.91 seconds
Started Jul 28 05:14:55 PM PDT 24
Finished Jul 28 05:14:56 PM PDT 24
Peak memory 197164 kb
Host smart-3fa0bd30-fb14-4069-9959-56863fc8604f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325663101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.325663101
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.90654603
Short name T555
Test name
Test status
Simulation time 1014681561 ps
CPU time 25.01 seconds
Started Jul 28 05:14:55 PM PDT 24
Finished Jul 28 05:15:20 PM PDT 24
Peak memory 195988 kb
Host smart-7502d3ed-6e4c-42a0-838b-25eab253845d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90654603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stress
.90654603
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.4160260923
Short name T399
Test name
Test status
Simulation time 182286798 ps
CPU time 0.82 seconds
Started Jul 28 05:14:54 PM PDT 24
Finished Jul 28 05:14:56 PM PDT 24
Peak memory 197432 kb
Host smart-9b4c0052-380b-47fa-a444-ebf46dd6eb2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160260923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.4160260923
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.1073060418
Short name T448
Test name
Test status
Simulation time 114804383 ps
CPU time 0.95 seconds
Started Jul 28 05:15:07 PM PDT 24
Finished Jul 28 05:15:08 PM PDT 24
Peak memory 196528 kb
Host smart-8101bf51-db8e-4d0b-ac9c-366b12965b60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073060418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.1073060418
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.723764826
Short name T573
Test name
Test status
Simulation time 46544441 ps
CPU time 1.1 seconds
Started Jul 28 05:14:51 PM PDT 24
Finished Jul 28 05:14:52 PM PDT 24
Peak memory 197804 kb
Host smart-7a1f68be-4b9f-4caf-8c48-98ce26dc1b7b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723764826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.723764826
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3810793617
Short name T283
Test name
Test status
Simulation time 226440280 ps
CPU time 1.78 seconds
Started Jul 28 05:15:00 PM PDT 24
Finished Jul 28 05:15:02 PM PDT 24
Peak memory 196340 kb
Host smart-786ebdb7-862f-45bf-b3ba-60e9a77aea02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810793617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3810793617
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3764512043
Short name T632
Test name
Test status
Simulation time 116256060 ps
CPU time 0.93 seconds
Started Jul 28 05:15:03 PM PDT 24
Finished Jul 28 05:15:04 PM PDT 24
Peak memory 197120 kb
Host smart-16da0eac-044c-4d82-818d-9bd03b012b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764512043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3764512043
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.4240344009
Short name T249
Test name
Test status
Simulation time 326397311 ps
CPU time 1.15 seconds
Started Jul 28 05:15:01 PM PDT 24
Finished Jul 28 05:15:02 PM PDT 24
Peak memory 196544 kb
Host smart-4e506920-24d9-4527-b98e-95b075b909c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240344009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.4240344009
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.4253692220
Short name T427
Test name
Test status
Simulation time 140019815 ps
CPU time 2.15 seconds
Started Jul 28 05:14:57 PM PDT 24
Finished Jul 28 05:15:00 PM PDT 24
Peak memory 198440 kb
Host smart-786ac596-8137-4a15-8c6f-e3c774c916a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253692220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.4253692220
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.547124819
Short name T90
Test name
Test status
Simulation time 65734187 ps
CPU time 0.8 seconds
Started Jul 28 05:14:52 PM PDT 24
Finished Jul 28 05:14:53 PM PDT 24
Peak memory 196356 kb
Host smart-de1af8e7-e91e-4005-bbca-c9be984a5a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547124819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.547124819
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.119265741
Short name T117
Test name
Test status
Simulation time 587384300 ps
CPU time 1.42 seconds
Started Jul 28 05:14:54 PM PDT 24
Finished Jul 28 05:14:55 PM PDT 24
Peak memory 197192 kb
Host smart-bdb7ad52-4322-4c07-ae97-91d9908d3227
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119265741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.119265741
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3950455708
Short name T222
Test name
Test status
Simulation time 5327357540 ps
CPU time 140.75 seconds
Started Jul 28 05:14:55 PM PDT 24
Finished Jul 28 05:17:16 PM PDT 24
Peak memory 198676 kb
Host smart-2b33e5a5-eadc-4463-91da-472c92c76110
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950455708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3950455708
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2771484639
Short name T544
Test name
Test status
Simulation time 32685701 ps
CPU time 0.57 seconds
Started Jul 28 05:14:49 PM PDT 24
Finished Jul 28 05:14:49 PM PDT 24
Peak memory 195292 kb
Host smart-8fc9fcb0-4915-4eb4-b42a-cce07d17ac68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771484639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2771484639
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.133275562
Short name T606
Test name
Test status
Simulation time 43545086 ps
CPU time 0.65 seconds
Started Jul 28 05:15:01 PM PDT 24
Finished Jul 28 05:15:02 PM PDT 24
Peak memory 194532 kb
Host smart-22a0c273-5279-40ac-8c62-ad767cd9b8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133275562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.133275562
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2100415778
Short name T538
Test name
Test status
Simulation time 1005094383 ps
CPU time 25.5 seconds
Started Jul 28 05:14:57 PM PDT 24
Finished Jul 28 05:15:23 PM PDT 24
Peak memory 197328 kb
Host smart-a8a5d7e7-b114-4186-8562-5554d72482d8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100415778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2100415778
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.19997063
Short name T113
Test name
Test status
Simulation time 67891601 ps
CPU time 0.89 seconds
Started Jul 28 05:15:02 PM PDT 24
Finished Jul 28 05:15:03 PM PDT 24
Peak memory 197476 kb
Host smart-0468c97d-4a40-4193-b434-e98ae6349066
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19997063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.19997063
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.4217274208
Short name T585
Test name
Test status
Simulation time 32963686 ps
CPU time 0.79 seconds
Started Jul 28 05:14:56 PM PDT 24
Finished Jul 28 05:14:57 PM PDT 24
Peak memory 195808 kb
Host smart-60b11e55-b1d3-4555-b5dc-48d765d6989e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217274208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.4217274208
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.3746129991
Short name T717
Test name
Test status
Simulation time 27647993 ps
CPU time 1.17 seconds
Started Jul 28 05:14:54 PM PDT 24
Finished Jul 28 05:14:56 PM PDT 24
Peak memory 197400 kb
Host smart-97dedc80-bb12-47de-8654-485b25d4777a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746129991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.3746129991
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.2433599950
Short name T576
Test name
Test status
Simulation time 180914423 ps
CPU time 1.58 seconds
Started Jul 28 05:15:09 PM PDT 24
Finished Jul 28 05:15:10 PM PDT 24
Peak memory 196984 kb
Host smart-6eba0280-786b-42af-99ea-6c946bdee639
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433599950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.2433599950
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.333316126
Short name T311
Test name
Test status
Simulation time 16917908 ps
CPU time 0.77 seconds
Started Jul 28 05:15:01 PM PDT 24
Finished Jul 28 05:15:02 PM PDT 24
Peak memory 195892 kb
Host smart-590ffa7f-d784-466f-aaaa-5f8ee5e76cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333316126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.333316126
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.2370063026
Short name T191
Test name
Test status
Simulation time 56740824 ps
CPU time 0.77 seconds
Started Jul 28 05:15:00 PM PDT 24
Finished Jul 28 05:15:01 PM PDT 24
Peak memory 195944 kb
Host smart-f62fd660-9b99-4c1e-a752-6df3f306d15f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370063026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.2370063026
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.223640245
Short name T518
Test name
Test status
Simulation time 504909867 ps
CPU time 5.79 seconds
Started Jul 28 05:14:51 PM PDT 24
Finished Jul 28 05:14:57 PM PDT 24
Peak memory 198468 kb
Host smart-e630deb0-f04c-4440-b70f-ff05ac4cd9eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223640245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.223640245
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.2825462108
Short name T683
Test name
Test status
Simulation time 77928203 ps
CPU time 0.96 seconds
Started Jul 28 05:15:00 PM PDT 24
Finished Jul 28 05:15:01 PM PDT 24
Peak memory 196264 kb
Host smart-476dc6fb-0ec6-4627-a777-abb195b7ac0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825462108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.2825462108
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.540591739
Short name T106
Test name
Test status
Simulation time 205984158 ps
CPU time 0.85 seconds
Started Jul 28 05:14:55 PM PDT 24
Finished Jul 28 05:14:56 PM PDT 24
Peak memory 195700 kb
Host smart-61aab725-8b41-49af-8fdc-0e078ddc1000
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540591739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.540591739
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3475507097
Short name T481
Test name
Test status
Simulation time 59790547010 ps
CPU time 45.15 seconds
Started Jul 28 05:14:57 PM PDT 24
Finished Jul 28 05:15:43 PM PDT 24
Peak memory 198684 kb
Host smart-27e4286f-50e8-48f0-a763-586c9c23d605
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475507097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3475507097
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.220238476
Short name T599
Test name
Test status
Simulation time 72955307013 ps
CPU time 1904.38 seconds
Started Jul 28 05:15:00 PM PDT 24
Finished Jul 28 05:46:45 PM PDT 24
Peak memory 198724 kb
Host smart-e25c214e-e15c-4de8-9b8d-ed8049cf994d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=220238476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.220238476
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2379061585
Short name T340
Test name
Test status
Simulation time 30560782 ps
CPU time 0.56 seconds
Started Jul 28 05:15:02 PM PDT 24
Finished Jul 28 05:15:03 PM PDT 24
Peak memory 195120 kb
Host smart-46b43d31-b4b1-4404-8928-acfd38e2f29b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379061585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2379061585
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2771275948
Short name T487
Test name
Test status
Simulation time 193387528 ps
CPU time 0.98 seconds
Started Jul 28 05:14:53 PM PDT 24
Finished Jul 28 05:14:54 PM PDT 24
Peak memory 196380 kb
Host smart-66beeeb1-8028-456c-a3fe-0de0de8532f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771275948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2771275948
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.724615684
Short name T447
Test name
Test status
Simulation time 3513049152 ps
CPU time 11.99 seconds
Started Jul 28 05:14:53 PM PDT 24
Finished Jul 28 05:15:05 PM PDT 24
Peak memory 197484 kb
Host smart-280dcaad-826a-431d-8f23-f284019f7bc0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724615684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.724615684
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1516625914
Short name T677
Test name
Test status
Simulation time 79954888 ps
CPU time 0.61 seconds
Started Jul 28 05:15:06 PM PDT 24
Finished Jul 28 05:15:06 PM PDT 24
Peak memory 194792 kb
Host smart-fca22b04-6571-4279-8483-5ad793e16994
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516625914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1516625914
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.858340075
Short name T426
Test name
Test status
Simulation time 1413451654 ps
CPU time 1.34 seconds
Started Jul 28 05:14:50 PM PDT 24
Finished Jul 28 05:14:51 PM PDT 24
Peak memory 196168 kb
Host smart-1ec2589c-8d08-49cd-8292-ba6527f0a401
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858340075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.858340075
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2974592989
Short name T434
Test name
Test status
Simulation time 260630882 ps
CPU time 2.39 seconds
Started Jul 28 05:14:54 PM PDT 24
Finished Jul 28 05:14:57 PM PDT 24
Peak memory 198692 kb
Host smart-fa9b8b8b-0705-4ccf-b28e-90505e59e5cb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974592989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2974592989
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2703328621
Short name T596
Test name
Test status
Simulation time 443811724 ps
CPU time 2.49 seconds
Started Jul 28 05:14:51 PM PDT 24
Finished Jul 28 05:14:54 PM PDT 24
Peak memory 198576 kb
Host smart-3a6e064d-84f0-4158-a052-b56f4f19eb1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703328621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2703328621
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1646175363
Short name T285
Test name
Test status
Simulation time 19899342 ps
CPU time 0.66 seconds
Started Jul 28 05:15:02 PM PDT 24
Finished Jul 28 05:15:03 PM PDT 24
Peak memory 194724 kb
Host smart-ddcb0658-4968-456b-8788-1356713890ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646175363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1646175363
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.4188429903
Short name T120
Test name
Test status
Simulation time 18866369 ps
CPU time 0.79 seconds
Started Jul 28 05:14:52 PM PDT 24
Finished Jul 28 05:14:53 PM PDT 24
Peak memory 195872 kb
Host smart-4de0e547-4daf-4a0c-aad8-fd71e45b6fd4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188429903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.4188429903
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1742259604
Short name T276
Test name
Test status
Simulation time 178749030 ps
CPU time 2.96 seconds
Started Jul 28 05:15:06 PM PDT 24
Finished Jul 28 05:15:09 PM PDT 24
Peak memory 198456 kb
Host smart-807b3a07-6762-4e87-8af5-a83f808cf884
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742259604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.1742259604
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1558730588
Short name T245
Test name
Test status
Simulation time 171874505 ps
CPU time 1.4 seconds
Started Jul 28 05:14:56 PM PDT 24
Finished Jul 28 05:14:57 PM PDT 24
Peak memory 198484 kb
Host smart-10a6a2d5-8b2f-4818-ab81-fb96c1cd200e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558730588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1558730588
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1376768838
Short name T291
Test name
Test status
Simulation time 41303969 ps
CPU time 0.87 seconds
Started Jul 28 05:14:58 PM PDT 24
Finished Jul 28 05:14:59 PM PDT 24
Peak memory 197576 kb
Host smart-b6fcd8e1-6ed1-4fcf-a4e8-72465081b022
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376768838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1376768838
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2889233812
Short name T597
Test name
Test status
Simulation time 16138632243 ps
CPU time 230.22 seconds
Started Jul 28 05:14:56 PM PDT 24
Finished Jul 28 05:18:46 PM PDT 24
Peak memory 198632 kb
Host smart-8b346ad6-8305-4813-9ab1-f15e6e40a71a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889233812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2889233812
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.1820163646
Short name T29
Test name
Test status
Simulation time 107259620795 ps
CPU time 2638.62 seconds
Started Jul 28 05:14:55 PM PDT 24
Finished Jul 28 05:58:54 PM PDT 24
Peak memory 198768 kb
Host smart-41da0233-4bc3-49c0-ac0f-de497fc2a1e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1820163646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.1820163646
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1736320900
Short name T213
Test name
Test status
Simulation time 94882632 ps
CPU time 0.58 seconds
Started Jul 28 05:14:59 PM PDT 24
Finished Jul 28 05:14:59 PM PDT 24
Peak memory 194600 kb
Host smart-70074941-d40b-4f37-a092-972a6290b8f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736320900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1736320900
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1617525183
Short name T656
Test name
Test status
Simulation time 118572295 ps
CPU time 0.92 seconds
Started Jul 28 05:15:06 PM PDT 24
Finished Jul 28 05:15:08 PM PDT 24
Peak memory 196540 kb
Host smart-b13c911b-29e8-430f-8f59-164b3b49ecb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617525183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1617525183
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1531807084
Short name T491
Test name
Test status
Simulation time 1108912404 ps
CPU time 21.13 seconds
Started Jul 28 05:14:57 PM PDT 24
Finished Jul 28 05:15:18 PM PDT 24
Peak memory 196044 kb
Host smart-c9859b97-a810-4dc2-b310-26882837e87e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531807084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1531807084
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2112846328
Short name T187
Test name
Test status
Simulation time 32523469 ps
CPU time 0.67 seconds
Started Jul 28 05:15:12 PM PDT 24
Finished Jul 28 05:15:13 PM PDT 24
Peak memory 195832 kb
Host smart-497946f4-1203-41ac-855b-6af94db99f01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112846328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2112846328
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.3543732323
Short name T665
Test name
Test status
Simulation time 29916664 ps
CPU time 0.7 seconds
Started Jul 28 05:15:15 PM PDT 24
Finished Jul 28 05:15:16 PM PDT 24
Peak memory 195760 kb
Host smart-de3e9e47-1633-475a-815e-31dade6f5b5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543732323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.3543732323
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1591466127
Short name T392
Test name
Test status
Simulation time 69601472 ps
CPU time 2.59 seconds
Started Jul 28 05:15:18 PM PDT 24
Finished Jul 28 05:15:20 PM PDT 24
Peak memory 198736 kb
Host smart-d350af31-9095-4351-b871-a6ef61e04eda
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591466127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1591466127
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1079637357
Short name T592
Test name
Test status
Simulation time 24513235 ps
CPU time 0.86 seconds
Started Jul 28 05:14:51 PM PDT 24
Finished Jul 28 05:14:52 PM PDT 24
Peak memory 195404 kb
Host smart-b05bbae5-2d77-406c-9ae4-74b020767ffc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079637357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1079637357
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.171843547
Short name T507
Test name
Test status
Simulation time 77285348 ps
CPU time 1.28 seconds
Started Jul 28 05:15:12 PM PDT 24
Finished Jul 28 05:15:13 PM PDT 24
Peak memory 196356 kb
Host smart-899f96a1-6f5c-4e8b-8148-9d1b9366c59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171843547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.171843547
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.762272716
Short name T162
Test name
Test status
Simulation time 115539362 ps
CPU time 1.13 seconds
Started Jul 28 05:15:07 PM PDT 24
Finished Jul 28 05:15:09 PM PDT 24
Peak memory 198552 kb
Host smart-14ba65d5-dcd9-4c57-b8c4-38475a23cf21
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762272716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullup
_pulldown.762272716
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2188131337
Short name T457
Test name
Test status
Simulation time 52273878 ps
CPU time 1.17 seconds
Started Jul 28 05:14:53 PM PDT 24
Finished Jul 28 05:14:54 PM PDT 24
Peak memory 198360 kb
Host smart-607bbf58-0e3f-4ce6-ba9a-5350b344fc58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188131337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.2188131337
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.4064248175
Short name T143
Test name
Test status
Simulation time 192484082 ps
CPU time 1.33 seconds
Started Jul 28 05:15:00 PM PDT 24
Finished Jul 28 05:15:02 PM PDT 24
Peak memory 196004 kb
Host smart-c72ea1f1-c49f-4fc8-9253-51f049e44cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064248175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.4064248175
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.751285797
Short name T708
Test name
Test status
Simulation time 26157036 ps
CPU time 0.89 seconds
Started Jul 28 05:14:56 PM PDT 24
Finished Jul 28 05:14:57 PM PDT 24
Peak memory 195804 kb
Host smart-59dced60-f809-427c-a480-db4a214651b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751285797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.751285797
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.537530081
Short name T132
Test name
Test status
Simulation time 11434530070 ps
CPU time 152.12 seconds
Started Jul 28 05:14:54 PM PDT 24
Finished Jul 28 05:17:26 PM PDT 24
Peak memory 198604 kb
Host smart-a9525364-9ea1-4a8a-8573-96449b202e83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537530081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.g
pio_stress_all.537530081
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.548660455
Short name T694
Test name
Test status
Simulation time 18695371 ps
CPU time 0.55 seconds
Started Jul 28 05:15:06 PM PDT 24
Finished Jul 28 05:15:07 PM PDT 24
Peak memory 195044 kb
Host smart-96dcfd6e-dbff-45e9-9bfa-be4ba8160070
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548660455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.548660455
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.698151496
Short name T204
Test name
Test status
Simulation time 37744372 ps
CPU time 0.9 seconds
Started Jul 28 05:15:14 PM PDT 24
Finished Jul 28 05:15:15 PM PDT 24
Peak memory 197020 kb
Host smart-b33d56b6-8884-4788-9906-7daf8f45c900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698151496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.698151496
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.950034073
Short name T273
Test name
Test status
Simulation time 1696589775 ps
CPU time 9.26 seconds
Started Jul 28 05:14:55 PM PDT 24
Finished Jul 28 05:15:10 PM PDT 24
Peak memory 197500 kb
Host smart-b3959091-1b8a-4aee-8bb7-c05e1c6b219e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950034073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.950034073
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.4174175544
Short name T675
Test name
Test status
Simulation time 61741060 ps
CPU time 1.01 seconds
Started Jul 28 05:14:55 PM PDT 24
Finished Jul 28 05:14:56 PM PDT 24
Peak memory 196864 kb
Host smart-a64c33ee-72ee-489b-af21-8d67c94737b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174175544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.4174175544
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1602881022
Short name T602
Test name
Test status
Simulation time 357207295 ps
CPU time 1.24 seconds
Started Jul 28 05:15:06 PM PDT 24
Finished Jul 28 05:15:08 PM PDT 24
Peak memory 197448 kb
Host smart-86ab6202-b5c6-45ab-aa70-fae4945e1744
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602881022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1602881022
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.782863614
Short name T234
Test name
Test status
Simulation time 39721419 ps
CPU time 1.73 seconds
Started Jul 28 05:15:01 PM PDT 24
Finished Jul 28 05:15:03 PM PDT 24
Peak memory 198496 kb
Host smart-61469bba-7bd0-4362-8d2d-7ef67223cd4b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782863614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.782863614
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1234047637
Short name T635
Test name
Test status
Simulation time 239201352 ps
CPU time 3.69 seconds
Started Jul 28 05:15:13 PM PDT 24
Finished Jul 28 05:15:17 PM PDT 24
Peak memory 198488 kb
Host smart-b252d2df-ad4a-410f-96f4-f7a45e7b235b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234047637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1234047637
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.1765783597
Short name T496
Test name
Test status
Simulation time 168714645 ps
CPU time 0.93 seconds
Started Jul 28 05:15:03 PM PDT 24
Finished Jul 28 05:15:04 PM PDT 24
Peak memory 196296 kb
Host smart-048efb18-1616-4b6e-a5f0-0ea23a44fc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765783597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.1765783597
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1749400185
Short name T614
Test name
Test status
Simulation time 30671555 ps
CPU time 0.71 seconds
Started Jul 28 05:15:07 PM PDT 24
Finished Jul 28 05:15:08 PM PDT 24
Peak memory 195908 kb
Host smart-8e04408e-260c-4f63-be53-fa44a12489ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749400185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1749400185
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1688714756
Short name T395
Test name
Test status
Simulation time 460377721 ps
CPU time 5.03 seconds
Started Jul 28 05:15:14 PM PDT 24
Finished Jul 28 05:15:19 PM PDT 24
Peak memory 198068 kb
Host smart-41faa9f3-d68c-485b-9f67-d75a2cebf13f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688714756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1688714756
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.3186693876
Short name T206
Test name
Test status
Simulation time 202615408 ps
CPU time 1.09 seconds
Started Jul 28 05:14:52 PM PDT 24
Finished Jul 28 05:14:53 PM PDT 24
Peak memory 196912 kb
Host smart-d3bfcd40-2031-4874-84e0-03dd2aae80b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186693876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3186693876
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3745747669
Short name T668
Test name
Test status
Simulation time 93302919 ps
CPU time 1.07 seconds
Started Jul 28 05:15:10 PM PDT 24
Finished Jul 28 05:15:11 PM PDT 24
Peak memory 196016 kb
Host smart-3015abae-1607-4bd1-b0c4-9d2fd04dba34
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745747669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3745747669
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.2064983507
Short name T483
Test name
Test status
Simulation time 28600695765 ps
CPU time 132.13 seconds
Started Jul 28 05:15:00 PM PDT 24
Finished Jul 28 05:17:12 PM PDT 24
Peak memory 198552 kb
Host smart-153d8e59-3055-4ef2-9049-57d009e05ebe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064983507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.2064983507
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.3411204325
Short name T177
Test name
Test status
Simulation time 39393198 ps
CPU time 0.54 seconds
Started Jul 28 05:15:10 PM PDT 24
Finished Jul 28 05:15:11 PM PDT 24
Peak memory 194432 kb
Host smart-fa74f7e1-a9bf-460b-bae0-981aa4151b2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411204325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3411204325
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3403931244
Short name T181
Test name
Test status
Simulation time 47233220 ps
CPU time 0.86 seconds
Started Jul 28 05:14:54 PM PDT 24
Finished Jul 28 05:14:55 PM PDT 24
Peak memory 196804 kb
Host smart-2ad555a1-7425-436f-b302-f5600f6f2a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403931244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3403931244
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3003125573
Short name T27
Test name
Test status
Simulation time 1213031888 ps
CPU time 8.11 seconds
Started Jul 28 05:15:03 PM PDT 24
Finished Jul 28 05:15:11 PM PDT 24
Peak memory 197472 kb
Host smart-a27c4f90-0d8b-4d5e-a6fd-0865083a15c3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003125573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3003125573
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.3607220421
Short name T238
Test name
Test status
Simulation time 35921325 ps
CPU time 0.72 seconds
Started Jul 28 05:15:00 PM PDT 24
Finished Jul 28 05:15:01 PM PDT 24
Peak memory 195004 kb
Host smart-a583a39d-80c5-48da-b737-c608b2662571
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607220421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.3607220421
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.824223243
Short name T259
Test name
Test status
Simulation time 115873746 ps
CPU time 1.33 seconds
Started Jul 28 05:15:05 PM PDT 24
Finished Jul 28 05:15:07 PM PDT 24
Peak memory 198532 kb
Host smart-9ff742a3-4043-4660-9830-3b51ed208c94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824223243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.824223243
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2892753251
Short name T710
Test name
Test status
Simulation time 40780234 ps
CPU time 1.67 seconds
Started Jul 28 05:15:04 PM PDT 24
Finished Jul 28 05:15:06 PM PDT 24
Peak memory 197448 kb
Host smart-29437f2a-1d8b-4f1b-9806-8cd9ad710232
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892753251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2892753251
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2683111848
Short name T616
Test name
Test status
Simulation time 216379266 ps
CPU time 1.4 seconds
Started Jul 28 05:14:58 PM PDT 24
Finished Jul 28 05:15:00 PM PDT 24
Peak memory 197304 kb
Host smart-5fe7ccd2-12e8-408a-a84d-f8da9d1c7ea6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683111848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2683111848
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.634818522
Short name T208
Test name
Test status
Simulation time 14275926 ps
CPU time 0.62 seconds
Started Jul 28 05:14:58 PM PDT 24
Finished Jul 28 05:14:59 PM PDT 24
Peak memory 194704 kb
Host smart-de062407-ec03-44d3-b7cf-373c3ae2405a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634818522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.634818522
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3195094237
Short name T539
Test name
Test status
Simulation time 43340947 ps
CPU time 0.88 seconds
Started Jul 28 05:15:02 PM PDT 24
Finished Jul 28 05:15:03 PM PDT 24
Peak memory 196264 kb
Host smart-c913d1a7-72a1-4bb4-9e2e-ccbd1b270dd3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195094237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3195094237
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1503077853
Short name T344
Test name
Test status
Simulation time 416349748 ps
CPU time 4.3 seconds
Started Jul 28 05:15:09 PM PDT 24
Finished Jul 28 05:15:14 PM PDT 24
Peak memory 198408 kb
Host smart-7bbf6133-0a46-48e9-93cd-90cd57bc0d17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503077853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1503077853
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2295436185
Short name T252
Test name
Test status
Simulation time 57545607 ps
CPU time 0.86 seconds
Started Jul 28 05:14:54 PM PDT 24
Finished Jul 28 05:14:55 PM PDT 24
Peak memory 197700 kb
Host smart-a2c16039-624d-439d-ae38-28d599dd81ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295436185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2295436185
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.541113222
Short name T358
Test name
Test status
Simulation time 56083415 ps
CPU time 1.07 seconds
Started Jul 28 05:14:56 PM PDT 24
Finished Jul 28 05:14:58 PM PDT 24
Peak memory 196264 kb
Host smart-965a3c30-b4f4-4c21-995d-a8e3e3675f89
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541113222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.541113222
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.600562791
Short name T335
Test name
Test status
Simulation time 2420762880 ps
CPU time 31.8 seconds
Started Jul 28 05:15:09 PM PDT 24
Finished Jul 28 05:15:41 PM PDT 24
Peak memory 198636 kb
Host smart-5c04888f-4f00-4a7e-bc44-fe9041730198
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600562791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.g
pio_stress_all.600562791
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3455491120
Short name T339
Test name
Test status
Simulation time 10191483 ps
CPU time 0.57 seconds
Started Jul 28 05:15:01 PM PDT 24
Finished Jul 28 05:15:02 PM PDT 24
Peak memory 194416 kb
Host smart-f4327063-f275-4073-99bf-46005172ab5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455491120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3455491120
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.976355634
Short name T153
Test name
Test status
Simulation time 24206377 ps
CPU time 0.79 seconds
Started Jul 28 05:14:55 PM PDT 24
Finished Jul 28 05:14:56 PM PDT 24
Peak memory 195876 kb
Host smart-8f9e0718-ef6d-4cc0-8638-6bacf6a3e05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976355634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.976355634
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1911422743
Short name T511
Test name
Test status
Simulation time 200125895 ps
CPU time 10.84 seconds
Started Jul 28 05:15:10 PM PDT 24
Finished Jul 28 05:15:21 PM PDT 24
Peak memory 196684 kb
Host smart-82b74309-0bcb-406c-af62-c3f4727a66be
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911422743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1911422743
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.3910691488
Short name T482
Test name
Test status
Simulation time 57307229 ps
CPU time 0.82 seconds
Started Jul 28 05:15:14 PM PDT 24
Finished Jul 28 05:15:15 PM PDT 24
Peak memory 196280 kb
Host smart-5bae12d8-a348-41e0-bb0b-980e792f2738
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910691488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3910691488
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2904803148
Short name T360
Test name
Test status
Simulation time 238615239 ps
CPU time 1.16 seconds
Started Jul 28 05:15:07 PM PDT 24
Finished Jul 28 05:15:08 PM PDT 24
Peak memory 197372 kb
Host smart-9345ef40-29a9-4cd7-8f9d-b56674f59d0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904803148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2904803148
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3610625737
Short name T352
Test name
Test status
Simulation time 19544319 ps
CPU time 0.88 seconds
Started Jul 28 05:14:58 PM PDT 24
Finished Jul 28 05:14:59 PM PDT 24
Peak memory 196540 kb
Host smart-9e9ecae1-acf9-4374-8a90-17229c690cde
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610625737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3610625737
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3062467089
Short name T552
Test name
Test status
Simulation time 258883068 ps
CPU time 1.59 seconds
Started Jul 28 05:14:58 PM PDT 24
Finished Jul 28 05:15:00 PM PDT 24
Peak memory 196656 kb
Host smart-75f051dd-bbe9-49c6-b062-0133f5cb7338
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062467089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3062467089
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1150298912
Short name T109
Test name
Test status
Simulation time 87067358 ps
CPU time 0.91 seconds
Started Jul 28 05:15:04 PM PDT 24
Finished Jul 28 05:15:05 PM PDT 24
Peak memory 196332 kb
Host smart-45cc891e-6489-4fda-b360-0e42eb74c06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150298912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1150298912
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.568540211
Short name T299
Test name
Test status
Simulation time 159183052 ps
CPU time 0.92 seconds
Started Jul 28 05:15:18 PM PDT 24
Finished Jul 28 05:15:19 PM PDT 24
Peak memory 196444 kb
Host smart-0d5c3801-9353-43b3-bd62-70af6cf3d0cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568540211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup
_pulldown.568540211
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.3120241613
Short name T10
Test name
Test status
Simulation time 899458746 ps
CPU time 2.96 seconds
Started Jul 28 05:14:57 PM PDT 24
Finished Jul 28 05:15:00 PM PDT 24
Peak memory 198504 kb
Host smart-485f5c53-52c1-4bb7-900f-bcd5e6efe097
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120241613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.3120241613
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.112489684
Short name T613
Test name
Test status
Simulation time 206750575 ps
CPU time 1.15 seconds
Started Jul 28 05:15:06 PM PDT 24
Finished Jul 28 05:15:07 PM PDT 24
Peak memory 197260 kb
Host smart-e61cb72a-51f6-48cd-8afe-3a40deb991e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112489684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.112489684
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2882036017
Short name T176
Test name
Test status
Simulation time 110825318 ps
CPU time 1.14 seconds
Started Jul 28 05:15:07 PM PDT 24
Finished Jul 28 05:15:08 PM PDT 24
Peak memory 196296 kb
Host smart-fab56b76-8d69-49b2-9944-8508f190d726
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882036017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2882036017
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3495235992
Short name T329
Test name
Test status
Simulation time 13218864725 ps
CPU time 166.33 seconds
Started Jul 28 05:15:11 PM PDT 24
Finished Jul 28 05:17:58 PM PDT 24
Peak memory 198572 kb
Host smart-0a5d397a-2f3d-4659-8490-d0d197656faa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495235992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3495235992
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.2099294304
Short name T472
Test name
Test status
Simulation time 13822972 ps
CPU time 0.58 seconds
Started Jul 28 05:13:49 PM PDT 24
Finished Jul 28 05:13:49 PM PDT 24
Peak memory 194392 kb
Host smart-45908292-3d04-44a5-9a78-43a7b9fe07c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099294304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2099294304
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2092446890
Short name T464
Test name
Test status
Simulation time 42371173 ps
CPU time 0.69 seconds
Started Jul 28 05:13:31 PM PDT 24
Finished Jul 28 05:13:32 PM PDT 24
Peak memory 194632 kb
Host smart-d46c42f5-389b-4405-88d0-d2d7a81d9545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092446890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2092446890
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.3867205242
Short name T171
Test name
Test status
Simulation time 4224084153 ps
CPU time 19.14 seconds
Started Jul 28 05:13:42 PM PDT 24
Finished Jul 28 05:14:01 PM PDT 24
Peak memory 197376 kb
Host smart-3dc26b5e-76b2-497a-8b35-57974f90f175
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867205242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.3867205242
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.510100956
Short name T443
Test name
Test status
Simulation time 76171591 ps
CPU time 0.99 seconds
Started Jul 28 05:13:48 PM PDT 24
Finished Jul 28 05:13:50 PM PDT 24
Peak memory 197632 kb
Host smart-96a56d04-ce91-42bc-8cbe-184120e720fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510100956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.510100956
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.2842064308
Short name T626
Test name
Test status
Simulation time 135909109 ps
CPU time 1.09 seconds
Started Jul 28 05:13:45 PM PDT 24
Finished Jul 28 05:13:46 PM PDT 24
Peak memory 197316 kb
Host smart-fb73dcd4-4eab-4ccf-a1d5-13a700b5e18d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842064308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.2842064308
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.1526422705
Short name T269
Test name
Test status
Simulation time 246002608 ps
CPU time 2.51 seconds
Started Jul 28 05:13:50 PM PDT 24
Finished Jul 28 05:13:52 PM PDT 24
Peak memory 198512 kb
Host smart-914c6396-ffd4-4576-90b5-a88647a92b8d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526422705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.1526422705
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.1272595518
Short name T698
Test name
Test status
Simulation time 341191161 ps
CPU time 2.77 seconds
Started Jul 28 05:13:46 PM PDT 24
Finished Jul 28 05:13:49 PM PDT 24
Peak memory 196460 kb
Host smart-b7853072-0231-49d9-8ffe-30a4ed191429
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272595518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
1272595518
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3559044448
Short name T317
Test name
Test status
Simulation time 61337849 ps
CPU time 1.12 seconds
Started Jul 28 05:13:37 PM PDT 24
Finished Jul 28 05:13:38 PM PDT 24
Peak memory 196456 kb
Host smart-6c16a9e9-5604-4bec-abe8-6581fd6b5617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559044448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3559044448
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1564437516
Short name T98
Test name
Test status
Simulation time 47348801 ps
CPU time 1.08 seconds
Started Jul 28 05:13:58 PM PDT 24
Finished Jul 28 05:13:59 PM PDT 24
Peak memory 197296 kb
Host smart-6c9ba1dd-0365-4ac9-a5af-8b0b97256992
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564437516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1564437516
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2689987172
Short name T321
Test name
Test status
Simulation time 308961943 ps
CPU time 2.64 seconds
Started Jul 28 05:13:37 PM PDT 24
Finished Jul 28 05:13:40 PM PDT 24
Peak memory 198476 kb
Host smart-cfa369c1-c39c-414c-8c47-6e2b7fa62974
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689987172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2689987172
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.894528811
Short name T644
Test name
Test status
Simulation time 78076452 ps
CPU time 1.37 seconds
Started Jul 28 05:14:00 PM PDT 24
Finished Jul 28 05:14:01 PM PDT 24
Peak memory 198524 kb
Host smart-fc7e3690-6216-48d5-a060-9adcb28999b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894528811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.894528811
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.4178168882
Short name T154
Test name
Test status
Simulation time 81857535 ps
CPU time 1.25 seconds
Started Jul 28 05:13:33 PM PDT 24
Finished Jul 28 05:13:35 PM PDT 24
Peak memory 197276 kb
Host smart-80c26152-9a38-4306-a5e3-840a3e354e42
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178168882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.4178168882
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1042030456
Short name T712
Test name
Test status
Simulation time 6968743793 ps
CPU time 73.66 seconds
Started Jul 28 05:13:37 PM PDT 24
Finished Jul 28 05:14:51 PM PDT 24
Peak memory 198640 kb
Host smart-dd2117fe-2175-47f8-80c4-3434cc4fa950
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042030456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1042030456
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2230503660
Short name T371
Test name
Test status
Simulation time 17901655 ps
CPU time 0.6 seconds
Started Jul 28 05:13:43 PM PDT 24
Finished Jul 28 05:13:44 PM PDT 24
Peak memory 195300 kb
Host smart-c40aee05-1bd6-4253-a8a4-186d69b96e05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230503660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2230503660
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.293203037
Short name T257
Test name
Test status
Simulation time 27432487 ps
CPU time 0.74 seconds
Started Jul 28 05:13:59 PM PDT 24
Finished Jul 28 05:14:00 PM PDT 24
Peak memory 195692 kb
Host smart-8ff17330-c3d2-4350-940e-47621a817e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293203037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.293203037
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3842170166
Short name T343
Test name
Test status
Simulation time 8808327021 ps
CPU time 17.94 seconds
Started Jul 28 05:13:46 PM PDT 24
Finished Jul 28 05:14:04 PM PDT 24
Peak memory 197268 kb
Host smart-58a533fb-6815-452d-8097-c7bc99146f2c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842170166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3842170166
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3438869728
Short name T280
Test name
Test status
Simulation time 63456600 ps
CPU time 0.92 seconds
Started Jul 28 05:13:43 PM PDT 24
Finished Jul 28 05:13:45 PM PDT 24
Peak memory 196852 kb
Host smart-8abe4427-4cbb-4206-9e29-6cef0ba957fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438869728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3438869728
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.4053193422
Short name T284
Test name
Test status
Simulation time 31043518 ps
CPU time 0.72 seconds
Started Jul 28 05:13:54 PM PDT 24
Finished Jul 28 05:13:54 PM PDT 24
Peak memory 194688 kb
Host smart-06531d90-9486-4bc5-9e69-5c0d3d062383
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053193422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.4053193422
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2720729776
Short name T359
Test name
Test status
Simulation time 18992544 ps
CPU time 0.94 seconds
Started Jul 28 05:13:51 PM PDT 24
Finished Jul 28 05:13:52 PM PDT 24
Peak memory 196548 kb
Host smart-623bbf20-62fc-4441-9241-00c9b7450663
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720729776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2720729776
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3118679114
Short name T685
Test name
Test status
Simulation time 66097162 ps
CPU time 1.11 seconds
Started Jul 28 05:13:39 PM PDT 24
Finished Jul 28 05:13:40 PM PDT 24
Peak memory 196240 kb
Host smart-24bdcaae-f17a-4924-be6a-2743260f93e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118679114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3118679114
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.570633798
Short name T415
Test name
Test status
Simulation time 86813362 ps
CPU time 0.92 seconds
Started Jul 28 05:13:48 PM PDT 24
Finished Jul 28 05:13:49 PM PDT 24
Peak memory 196388 kb
Host smart-4509d44c-9ba1-40c9-b1f6-99cc755c59c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570633798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.570633798
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.1888716194
Short name T707
Test name
Test status
Simulation time 220450344 ps
CPU time 0.74 seconds
Started Jul 28 05:13:47 PM PDT 24
Finished Jul 28 05:13:48 PM PDT 24
Peak memory 196480 kb
Host smart-b8129547-d81d-4311-845a-889a1265927a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888716194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.1888716194
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1674752635
Short name T622
Test name
Test status
Simulation time 839366180 ps
CPU time 3.44 seconds
Started Jul 28 05:13:42 PM PDT 24
Finished Jul 28 05:13:46 PM PDT 24
Peak memory 198504 kb
Host smart-e29bb529-a1a4-459c-8ac4-1116ed3256f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674752635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1674752635
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.2603361471
Short name T148
Test name
Test status
Simulation time 84461769 ps
CPU time 1.49 seconds
Started Jul 28 05:13:39 PM PDT 24
Finished Jul 28 05:13:41 PM PDT 24
Peak memory 197312 kb
Host smart-d9ddb316-bd6f-44a7-a504-2bde9f8b0453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603361471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2603361471
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.2597302269
Short name T574
Test name
Test status
Simulation time 176243864 ps
CPU time 1.03 seconds
Started Jul 28 05:13:56 PM PDT 24
Finished Jul 28 05:13:57 PM PDT 24
Peak memory 196892 kb
Host smart-98c8de29-2c3b-43fd-be0c-123479a922cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597302269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.2597302269
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.4171576249
Short name T326
Test name
Test status
Simulation time 4664094781 ps
CPU time 28.91 seconds
Started Jul 28 05:13:54 PM PDT 24
Finished Jul 28 05:14:23 PM PDT 24
Peak memory 198612 kb
Host smart-0f5ef7c7-57b7-4d67-aad3-b16bf1412772
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171576249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.4171576249
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.4276602635
Short name T633
Test name
Test status
Simulation time 14056945 ps
CPU time 0.55 seconds
Started Jul 28 05:13:59 PM PDT 24
Finished Jul 28 05:14:00 PM PDT 24
Peak memory 193888 kb
Host smart-42a44737-9c72-45ec-8b99-83c791c86789
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276602635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.4276602635
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3466818379
Short name T312
Test name
Test status
Simulation time 44753890 ps
CPU time 0.64 seconds
Started Jul 28 05:13:37 PM PDT 24
Finished Jul 28 05:13:38 PM PDT 24
Peak memory 194504 kb
Host smart-f8981b54-dad4-4020-a710-c735376ecda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466818379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3466818379
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1051326583
Short name T701
Test name
Test status
Simulation time 233508370 ps
CPU time 10.95 seconds
Started Jul 28 05:13:56 PM PDT 24
Finished Jul 28 05:14:07 PM PDT 24
Peak memory 197276 kb
Host smart-e8f1f506-1807-452b-a962-9a60df4a2445
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051326583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1051326583
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1792269525
Short name T225
Test name
Test status
Simulation time 128455069 ps
CPU time 0.7 seconds
Started Jul 28 05:13:54 PM PDT 24
Finished Jul 28 05:13:55 PM PDT 24
Peak memory 195148 kb
Host smart-8a8ff943-9605-4a19-862e-a2ff5e516a73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792269525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1792269525
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.4033109541
Short name T510
Test name
Test status
Simulation time 72596613 ps
CPU time 1.27 seconds
Started Jul 28 05:13:36 PM PDT 24
Finished Jul 28 05:13:38 PM PDT 24
Peak memory 198560 kb
Host smart-be9588e8-be60-4f47-a959-ebea0449b46f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033109541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.4033109541
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.790381872
Short name T424
Test name
Test status
Simulation time 102502496 ps
CPU time 1.12 seconds
Started Jul 28 05:13:40 PM PDT 24
Finished Jul 28 05:13:42 PM PDT 24
Peak memory 198352 kb
Host smart-20362983-c111-4a12-b61d-c2a3323c78a7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790381872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.790381872
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.166753498
Short name T324
Test name
Test status
Simulation time 168606351 ps
CPU time 2.1 seconds
Started Jul 28 05:13:39 PM PDT 24
Finished Jul 28 05:13:41 PM PDT 24
Peak memory 198600 kb
Host smart-4ac1ecbb-caaf-47de-8077-d6ad8c880bcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166753498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.166753498
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3055725279
Short name T459
Test name
Test status
Simulation time 190292326 ps
CPU time 0.97 seconds
Started Jul 28 05:13:32 PM PDT 24
Finished Jul 28 05:13:33 PM PDT 24
Peak memory 197168 kb
Host smart-1b35cfb3-8eab-404a-b41e-0d5ea955c39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055725279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3055725279
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3375816620
Short name T513
Test name
Test status
Simulation time 20975800 ps
CPU time 0.73 seconds
Started Jul 28 05:13:34 PM PDT 24
Finished Jul 28 05:13:35 PM PDT 24
Peak memory 195916 kb
Host smart-5e2af8af-d89c-49cb-b18d-d51ee6ef6228
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375816620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3375816620
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1069715061
Short name T530
Test name
Test status
Simulation time 241942652 ps
CPU time 3.21 seconds
Started Jul 28 05:13:43 PM PDT 24
Finished Jul 28 05:13:47 PM PDT 24
Peak memory 198460 kb
Host smart-837b5671-cf41-4382-b18f-66f7ef3a8bea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069715061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.1069715061
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.302745719
Short name T374
Test name
Test status
Simulation time 102629658 ps
CPU time 0.84 seconds
Started Jul 28 05:13:39 PM PDT 24
Finished Jul 28 05:13:40 PM PDT 24
Peak memory 197700 kb
Host smart-23914d90-b679-4045-9a12-4400e5b984ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302745719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.302745719
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3714238271
Short name T173
Test name
Test status
Simulation time 377358973 ps
CPU time 1.32 seconds
Started Jul 28 05:13:51 PM PDT 24
Finished Jul 28 05:13:53 PM PDT 24
Peak memory 196040 kb
Host smart-b2b52b44-22cb-4ae0-bd33-21d7f4266e53
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714238271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3714238271
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.3741744226
Short name T5
Test name
Test status
Simulation time 16336373517 ps
CPU time 175.25 seconds
Started Jul 28 05:13:37 PM PDT 24
Finished Jul 28 05:16:33 PM PDT 24
Peak memory 198496 kb
Host smart-10ba10cf-4644-4b39-ad27-3f8c8ae76895
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741744226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.3741744226
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.427993245
Short name T192
Test name
Test status
Simulation time 38156483 ps
CPU time 0.57 seconds
Started Jul 28 05:13:59 PM PDT 24
Finished Jul 28 05:14:00 PM PDT 24
Peak memory 194596 kb
Host smart-34cc2963-d226-41f6-8ed3-63120ccdedae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427993245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.427993245
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.2107903497
Short name T583
Test name
Test status
Simulation time 49872728 ps
CPU time 0.8 seconds
Started Jul 28 05:13:59 PM PDT 24
Finished Jul 28 05:14:00 PM PDT 24
Peak memory 195896 kb
Host smart-830cfcdc-150c-48ac-94bd-e883e4a0a53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107903497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.2107903497
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2771267206
Short name T620
Test name
Test status
Simulation time 812095217 ps
CPU time 26.65 seconds
Started Jul 28 05:13:41 PM PDT 24
Finished Jul 28 05:14:08 PM PDT 24
Peak memory 197436 kb
Host smart-d42be697-00ff-4d09-ba2f-c006bc7a8774
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771267206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2771267206
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.262927216
Short name T230
Test name
Test status
Simulation time 22271077 ps
CPU time 0.7 seconds
Started Jul 28 05:13:55 PM PDT 24
Finished Jul 28 05:13:56 PM PDT 24
Peak memory 195768 kb
Host smart-f012ebac-a3c9-44df-91a3-1b26e8fef03d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262927216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.262927216
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1430969200
Short name T231
Test name
Test status
Simulation time 252487563 ps
CPU time 1.15 seconds
Started Jul 28 05:13:51 PM PDT 24
Finished Jul 28 05:13:52 PM PDT 24
Peak memory 197340 kb
Host smart-1fc1fefb-37b9-484d-ae59-3a7d75010d36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430969200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1430969200
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.3615261810
Short name T649
Test name
Test status
Simulation time 130792758 ps
CPU time 2.62 seconds
Started Jul 28 05:13:49 PM PDT 24
Finished Jul 28 05:13:52 PM PDT 24
Peak memory 198544 kb
Host smart-4d515417-0886-4d14-aa63-ee77d1efe673
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615261810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.3615261810
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1289971464
Short name T567
Test name
Test status
Simulation time 527071616 ps
CPU time 1.58 seconds
Started Jul 28 05:14:04 PM PDT 24
Finished Jul 28 05:14:05 PM PDT 24
Peak memory 196576 kb
Host smart-a6622d99-de03-4f38-8495-f0127e02b524
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289971464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1289971464
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2291335065
Short name T560
Test name
Test status
Simulation time 26039124 ps
CPU time 1.01 seconds
Started Jul 28 05:13:46 PM PDT 24
Finished Jul 28 05:13:47 PM PDT 24
Peak memory 196424 kb
Host smart-2ffa0a5c-f0ad-4adf-86ca-6efb81bb3789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291335065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2291335065
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.666962953
Short name T436
Test name
Test status
Simulation time 64058957 ps
CPU time 1.36 seconds
Started Jul 28 05:13:52 PM PDT 24
Finished Jul 28 05:13:53 PM PDT 24
Peak memory 196336 kb
Host smart-b6a52e53-3ba5-4878-8b0b-c89acc0fe0bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666962953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_
pulldown.666962953
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1096551576
Short name T302
Test name
Test status
Simulation time 1142760602 ps
CPU time 3.84 seconds
Started Jul 28 05:13:45 PM PDT 24
Finished Jul 28 05:13:49 PM PDT 24
Peak memory 198424 kb
Host smart-58845487-b48f-468c-85b7-9bc1aaf5fc30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096551576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1096551576
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3815828405
Short name T277
Test name
Test status
Simulation time 99445898 ps
CPU time 0.85 seconds
Started Jul 28 05:13:43 PM PDT 24
Finished Jul 28 05:13:44 PM PDT 24
Peak memory 195840 kb
Host smart-29648e15-dc57-4a25-82ef-69edd345eddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815828405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3815828405
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3401943815
Short name T304
Test name
Test status
Simulation time 834626792 ps
CPU time 1.34 seconds
Started Jul 28 05:13:59 PM PDT 24
Finished Jul 28 05:14:01 PM PDT 24
Peak memory 196032 kb
Host smart-fc9f943f-dcb4-4f56-b08e-2834f306f0e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401943815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3401943815
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1634898424
Short name T116
Test name
Test status
Simulation time 22254045293 ps
CPU time 73.71 seconds
Started Jul 28 05:13:40 PM PDT 24
Finished Jul 28 05:14:54 PM PDT 24
Peak memory 198624 kb
Host smart-3d271737-7d12-4414-be72-886d683198e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634898424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1634898424
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.4058381778
Short name T674
Test name
Test status
Simulation time 20089516413 ps
CPU time 454.03 seconds
Started Jul 28 05:13:46 PM PDT 24
Finished Jul 28 05:21:21 PM PDT 24
Peak memory 198740 kb
Host smart-80104c95-3124-46c8-bb19-3ee8c1198751
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4058381778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.4058381778
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3857551395
Short name T659
Test name
Test status
Simulation time 12199569 ps
CPU time 0.56 seconds
Started Jul 28 05:13:45 PM PDT 24
Finished Jul 28 05:13:46 PM PDT 24
Peak memory 194368 kb
Host smart-8631fd82-8cbb-4de7-8439-14e14b9d9dc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857551395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3857551395
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3601655340
Short name T433
Test name
Test status
Simulation time 27983131 ps
CPU time 0.92 seconds
Started Jul 28 05:13:41 PM PDT 24
Finished Jul 28 05:13:42 PM PDT 24
Peak memory 196956 kb
Host smart-fcfa7849-d784-4fb8-9229-4896dd53bee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601655340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3601655340
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2287918532
Short name T572
Test name
Test status
Simulation time 1377533088 ps
CPU time 17.66 seconds
Started Jul 28 05:13:44 PM PDT 24
Finished Jul 28 05:14:01 PM PDT 24
Peak memory 198520 kb
Host smart-19fb522b-9bbd-4b77-a224-8bdd0d7727b7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287918532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2287918532
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.804497953
Short name T4
Test name
Test status
Simulation time 169799382 ps
CPU time 0.88 seconds
Started Jul 28 05:13:42 PM PDT 24
Finished Jul 28 05:13:43 PM PDT 24
Peak memory 197280 kb
Host smart-d87f3b55-e047-44a9-8275-9dbc3f1e1cd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804497953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.804497953
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.4012036332
Short name T233
Test name
Test status
Simulation time 38303807 ps
CPU time 0.84 seconds
Started Jul 28 05:13:44 PM PDT 24
Finished Jul 28 05:13:45 PM PDT 24
Peak memory 197132 kb
Host smart-e30d11e6-ad1e-4bf9-b92e-dd4aa240c141
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012036332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.4012036332
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.856355235
Short name T516
Test name
Test status
Simulation time 115301515 ps
CPU time 3.09 seconds
Started Jul 28 05:13:52 PM PDT 24
Finished Jul 28 05:13:55 PM PDT 24
Peak memory 198572 kb
Host smart-7efaf587-303d-47f8-adbb-99542f8015f0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856355235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.gpio_intr_with_filter_rand_intr_event.856355235
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3695703456
Short name T709
Test name
Test status
Simulation time 228176373 ps
CPU time 1.96 seconds
Started Jul 28 05:13:52 PM PDT 24
Finished Jul 28 05:13:54 PM PDT 24
Peak memory 198512 kb
Host smart-ff1824b4-7b63-4120-9055-156af8e8186a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695703456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3695703456
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1193455565
Short name T645
Test name
Test status
Simulation time 175682049 ps
CPU time 1.05 seconds
Started Jul 28 05:13:37 PM PDT 24
Finished Jul 28 05:13:38 PM PDT 24
Peak memory 197024 kb
Host smart-95d45403-2ef3-46a3-98b1-eadac719723e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193455565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1193455565
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.45205007
Short name T367
Test name
Test status
Simulation time 18332693 ps
CPU time 0.72 seconds
Started Jul 28 05:13:39 PM PDT 24
Finished Jul 28 05:13:40 PM PDT 24
Peak memory 195944 kb
Host smart-0220a6ad-7088-43a5-a30d-4ebaacb42581
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45205007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_p
ulldown.45205007
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1900573034
Short name T601
Test name
Test status
Simulation time 555556117 ps
CPU time 5.63 seconds
Started Jul 28 05:13:52 PM PDT 24
Finished Jul 28 05:13:58 PM PDT 24
Peak memory 198476 kb
Host smart-7201882f-b781-4421-b476-49c681c07de0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900573034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1900573034
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2260315370
Short name T571
Test name
Test status
Simulation time 133454551 ps
CPU time 0.96 seconds
Started Jul 28 05:13:35 PM PDT 24
Finished Jul 28 05:13:37 PM PDT 24
Peak memory 196260 kb
Host smart-8a433188-4ea7-452b-b576-df4792af8425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260315370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2260315370
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2351246385
Short name T219
Test name
Test status
Simulation time 130249750 ps
CPU time 1.32 seconds
Started Jul 28 05:13:47 PM PDT 24
Finished Jul 28 05:13:49 PM PDT 24
Peak memory 197104 kb
Host smart-68bb777d-7246-4cc8-b7a5-b5c957f1c2ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351246385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2351246385
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.108512725
Short name T163
Test name
Test status
Simulation time 28316555287 ps
CPU time 167.87 seconds
Started Jul 28 05:13:41 PM PDT 24
Finished Jul 28 05:16:29 PM PDT 24
Peak memory 198568 kb
Host smart-ef85661f-f3b6-4d5c-a1d0-f8acf1d8fb5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108512725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.108512725
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.4074244420
Short name T48
Test name
Test status
Simulation time 55654861366 ps
CPU time 1269.82 seconds
Started Jul 28 05:13:52 PM PDT 24
Finished Jul 28 05:35:03 PM PDT 24
Peak memory 198756 kb
Host smart-7857d35e-b9fa-45b3-b31b-26c2debc4cc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4074244420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.4074244420
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1151743900
Short name T938
Test name
Test status
Simulation time 68002128 ps
CPU time 1.17 seconds
Started Jul 28 05:11:44 PM PDT 24
Finished Jul 28 05:11:45 PM PDT 24
Peak memory 191788 kb
Host smart-6062e581-b073-4651-acd1-86736f99b554
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1151743900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.1151743900
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2877525590
Short name T900
Test name
Test status
Simulation time 134123129 ps
CPU time 1.16 seconds
Started Jul 28 05:11:54 PM PDT 24
Finished Jul 28 05:11:55 PM PDT 24
Peak memory 191776 kb
Host smart-350cc106-f8d4-4663-bf12-16f8b9a4f7aa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877525590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2877525590
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.48787665
Short name T902
Test name
Test status
Simulation time 53231332 ps
CPU time 1.01 seconds
Started Jul 28 05:11:55 PM PDT 24
Finished Jul 28 05:11:56 PM PDT 24
Peak memory 191812 kb
Host smart-30d5f2ae-45fd-4d6d-9fb2-e0d3f3523ada
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=48787665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.48787665
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.75347354
Short name T852
Test name
Test status
Simulation time 163501267 ps
CPU time 1.11 seconds
Started Jul 28 05:11:53 PM PDT 24
Finished Jul 28 05:11:54 PM PDT 24
Peak memory 191824 kb
Host smart-c36464b0-2b9f-4c32-bcdd-e9ac50ff7b5f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75347354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.75347354
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.98417439
Short name T844
Test name
Test status
Simulation time 92359212 ps
CPU time 0.9 seconds
Started Jul 28 05:11:51 PM PDT 24
Finished Jul 28 05:11:52 PM PDT 24
Peak memory 191572 kb
Host smart-aeb5af48-49f4-49b5-a8dc-c9d6bbe1f8be
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=98417439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.98417439
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1236948285
Short name T916
Test name
Test status
Simulation time 24211681 ps
CPU time 0.77 seconds
Started Jul 28 05:12:08 PM PDT 24
Finished Jul 28 05:12:09 PM PDT 24
Peak memory 191392 kb
Host smart-a5af51e2-58b8-452d-bbfb-e04936851a15
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236948285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1236948285
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1007352384
Short name T897
Test name
Test status
Simulation time 122321115 ps
CPU time 0.95 seconds
Started Jul 28 05:11:49 PM PDT 24
Finished Jul 28 05:11:50 PM PDT 24
Peak memory 191796 kb
Host smart-3d8284c4-5551-4e8d-8816-89cea6156e54
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1007352384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1007352384
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2515244599
Short name T871
Test name
Test status
Simulation time 492822430 ps
CPU time 1.38 seconds
Started Jul 28 05:11:36 PM PDT 24
Finished Jul 28 05:11:38 PM PDT 24
Peak memory 198204 kb
Host smart-7e59b7e0-31e2-4808-8d42-bc90ff21516a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515244599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2515244599
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1459019348
Short name T867
Test name
Test status
Simulation time 204423968 ps
CPU time 1.12 seconds
Started Jul 28 05:11:50 PM PDT 24
Finished Jul 28 05:11:51 PM PDT 24
Peak memory 191596 kb
Host smart-eaec7db2-93f3-428a-92d8-0ec1413c3816
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1459019348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1459019348
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2747211698
Short name T856
Test name
Test status
Simulation time 313055616 ps
CPU time 0.89 seconds
Started Jul 28 05:11:55 PM PDT 24
Finished Jul 28 05:11:56 PM PDT 24
Peak memory 191792 kb
Host smart-f650f922-74c6-428d-9b06-8abeba1502c6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747211698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2747211698
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2689099726
Short name T846
Test name
Test status
Simulation time 18941800 ps
CPU time 0.7 seconds
Started Jul 28 05:11:47 PM PDT 24
Finished Jul 28 05:11:48 PM PDT 24
Peak memory 191540 kb
Host smart-6ab7d8c6-c35b-406b-a21e-42df0f4c419d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2689099726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2689099726
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1928169277
Short name T913
Test name
Test status
Simulation time 156568011 ps
CPU time 0.85 seconds
Started Jul 28 05:11:38 PM PDT 24
Finished Jul 28 05:11:39 PM PDT 24
Peak memory 191620 kb
Host smart-94371ba0-fab4-41f5-a9b5-ae04d89e669b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928169277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1928169277
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.208095892
Short name T888
Test name
Test status
Simulation time 38538314 ps
CPU time 1.1 seconds
Started Jul 28 05:11:44 PM PDT 24
Finished Jul 28 05:11:45 PM PDT 24
Peak memory 191692 kb
Host smart-32328866-fe7d-4bca-8428-f2ba3011e298
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=208095892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.208095892
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1247657391
Short name T939
Test name
Test status
Simulation time 115753797 ps
CPU time 0.98 seconds
Started Jul 28 05:11:39 PM PDT 24
Finished Jul 28 05:11:40 PM PDT 24
Peak memory 191612 kb
Host smart-ef6bdb5d-7e18-4dc2-84ff-8904d77da701
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247657391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1247657391
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1644312885
Short name T917
Test name
Test status
Simulation time 127514330 ps
CPU time 0.99 seconds
Started Jul 28 05:11:49 PM PDT 24
Finished Jul 28 05:11:50 PM PDT 24
Peak memory 191788 kb
Host smart-af5e1c1c-db36-4ac8-a42d-76eabb63d67d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1644312885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1644312885
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4183540844
Short name T848
Test name
Test status
Simulation time 114577981 ps
CPU time 0.89 seconds
Started Jul 28 05:11:53 PM PDT 24
Finished Jul 28 05:11:54 PM PDT 24
Peak memory 191612 kb
Host smart-2e31bdb3-fb78-4da7-a871-416b29f2a420
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183540844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4183540844
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.4111036769
Short name T907
Test name
Test status
Simulation time 112489565 ps
CPU time 0.88 seconds
Started Jul 28 05:12:12 PM PDT 24
Finished Jul 28 05:12:13 PM PDT 24
Peak memory 197300 kb
Host smart-ae2c9f75-a308-4926-8524-63563d35170f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4111036769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.4111036769
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3651744798
Short name T885
Test name
Test status
Simulation time 66826792 ps
CPU time 1.01 seconds
Started Jul 28 05:11:36 PM PDT 24
Finished Jul 28 05:11:37 PM PDT 24
Peak memory 191724 kb
Host smart-010897de-d80c-47ce-b1e4-460463339e43
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651744798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3651744798
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1799286620
Short name T906
Test name
Test status
Simulation time 252317135 ps
CPU time 1.12 seconds
Started Jul 28 05:11:57 PM PDT 24
Finished Jul 28 05:11:58 PM PDT 24
Peak memory 191708 kb
Host smart-bc8b369d-9a95-406f-94f0-29bb309460c2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1799286620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1799286620
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3367936101
Short name T918
Test name
Test status
Simulation time 25529884 ps
CPU time 0.8 seconds
Started Jul 28 05:11:35 PM PDT 24
Finished Jul 28 05:11:36 PM PDT 24
Peak memory 196284 kb
Host smart-d8675d90-55a5-4371-a6bc-2fe22a95567b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367936101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3367936101
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3262301997
Short name T878
Test name
Test status
Simulation time 134459531 ps
CPU time 1.14 seconds
Started Jul 28 05:11:42 PM PDT 24
Finished Jul 28 05:11:43 PM PDT 24
Peak memory 198260 kb
Host smart-aa0d26e9-4279-42db-820a-01475eb5dded
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3262301997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.3262301997
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3057403711
Short name T934
Test name
Test status
Simulation time 74062846 ps
CPU time 1.32 seconds
Started Jul 28 05:12:04 PM PDT 24
Finished Jul 28 05:12:06 PM PDT 24
Peak memory 198160 kb
Host smart-2506bdee-4485-42f7-99d2-02017e0f30be
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057403711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3057403711
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1722161310
Short name T868
Test name
Test status
Simulation time 465429817 ps
CPU time 1.36 seconds
Started Jul 28 05:11:40 PM PDT 24
Finished Jul 28 05:11:41 PM PDT 24
Peak memory 192016 kb
Host smart-1d4b08c6-cafc-44cf-97fb-f8624710e38a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1722161310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.1722161310
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1168277311
Short name T920
Test name
Test status
Simulation time 86715437 ps
CPU time 1.04 seconds
Started Jul 28 05:11:42 PM PDT 24
Finished Jul 28 05:11:43 PM PDT 24
Peak memory 197912 kb
Host smart-af5756bc-94f6-497c-81e2-67d4de749fb2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168277311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1168277311
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2539858354
Short name T903
Test name
Test status
Simulation time 69621719 ps
CPU time 1.26 seconds
Started Jul 28 05:11:53 PM PDT 24
Finished Jul 28 05:11:54 PM PDT 24
Peak memory 191868 kb
Host smart-dc1bf3b8-b332-45bd-ad61-2085f3373aed
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2539858354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2539858354
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1465694918
Short name T879
Test name
Test status
Simulation time 53579170 ps
CPU time 1.12 seconds
Started Jul 28 05:11:45 PM PDT 24
Finished Jul 28 05:11:46 PM PDT 24
Peak memory 191712 kb
Host smart-ecbcac21-f04a-421e-9400-c4dc26b8bba5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465694918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1465694918
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2247499964
Short name T909
Test name
Test status
Simulation time 159095908 ps
CPU time 0.89 seconds
Started Jul 28 05:11:48 PM PDT 24
Finished Jul 28 05:11:49 PM PDT 24
Peak memory 191420 kb
Host smart-57449968-5e74-4511-a98e-374a0c2ba5ca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2247499964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2247499964
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4208980241
Short name T873
Test name
Test status
Simulation time 52924271 ps
CPU time 0.96 seconds
Started Jul 28 05:11:38 PM PDT 24
Finished Jul 28 05:11:39 PM PDT 24
Peak memory 191620 kb
Host smart-9f4ee0b4-b6a2-4ff0-a6af-32649a997472
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208980241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4208980241
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3215953904
Short name T927
Test name
Test status
Simulation time 42753410 ps
CPU time 0.95 seconds
Started Jul 28 05:11:55 PM PDT 24
Finished Jul 28 05:11:56 PM PDT 24
Peak memory 191428 kb
Host smart-e76db5e5-4f97-49bb-b4bc-4196e72350f7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3215953904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.3215953904
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3936706335
Short name T875
Test name
Test status
Simulation time 183360827 ps
CPU time 0.97 seconds
Started Jul 28 05:11:44 PM PDT 24
Finished Jul 28 05:11:45 PM PDT 24
Peak memory 191812 kb
Host smart-6516508e-b827-4e46-b134-f36b2bf4f278
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936706335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3936706335
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1024741992
Short name T923
Test name
Test status
Simulation time 445701072 ps
CPU time 1.42 seconds
Started Jul 28 05:11:55 PM PDT 24
Finished Jul 28 05:11:57 PM PDT 24
Peak memory 191636 kb
Host smart-7d99be03-45ca-430d-bdf6-1332568471bb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1024741992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1024741992
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.477873756
Short name T853
Test name
Test status
Simulation time 49744944 ps
CPU time 1.23 seconds
Started Jul 28 05:12:00 PM PDT 24
Finished Jul 28 05:12:01 PM PDT 24
Peak memory 191832 kb
Host smart-e0bdf152-7e98-4549-8858-ec0f19a5871b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477873756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.477873756
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1340217567
Short name T870
Test name
Test status
Simulation time 104150752 ps
CPU time 0.73 seconds
Started Jul 28 05:11:35 PM PDT 24
Finished Jul 28 05:11:36 PM PDT 24
Peak memory 191552 kb
Host smart-1d082b96-5bd5-4802-affa-47d766066425
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1340217567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1340217567
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3236958844
Short name T850
Test name
Test status
Simulation time 163219778 ps
CPU time 0.94 seconds
Started Jul 28 05:11:55 PM PDT 24
Finished Jul 28 05:11:56 PM PDT 24
Peak memory 197440 kb
Host smart-24d40fd4-dc25-409b-800b-4641a45df177
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236958844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3236958844
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.237521866
Short name T941
Test name
Test status
Simulation time 46095401 ps
CPU time 1.31 seconds
Started Jul 28 05:11:42 PM PDT 24
Finished Jul 28 05:11:44 PM PDT 24
Peak memory 191668 kb
Host smart-eceb794e-e428-433f-8b4b-f09c9f781066
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=237521866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.237521866
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2306122121
Short name T895
Test name
Test status
Simulation time 45408145 ps
CPU time 1.26 seconds
Started Jul 28 05:11:50 PM PDT 24
Finished Jul 28 05:11:51 PM PDT 24
Peak memory 191800 kb
Host smart-f3641877-55e2-4637-b53b-78bf57e49695
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306122121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2306122121
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.442445393
Short name T925
Test name
Test status
Simulation time 316587349 ps
CPU time 1.32 seconds
Started Jul 28 05:11:59 PM PDT 24
Finished Jul 28 05:12:01 PM PDT 24
Peak memory 191728 kb
Host smart-b461a3bc-1402-4785-ab85-e2ffc3605d16
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=442445393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.442445393
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3044594781
Short name T865
Test name
Test status
Simulation time 163102063 ps
CPU time 1.36 seconds
Started Jul 28 05:11:42 PM PDT 24
Finished Jul 28 05:11:44 PM PDT 24
Peak memory 191724 kb
Host smart-1946074c-f394-45f4-9c84-3c1d05a8b060
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044594781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3044594781
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3198064760
Short name T894
Test name
Test status
Simulation time 273357424 ps
CPU time 1.23 seconds
Started Jul 28 05:11:43 PM PDT 24
Finished Jul 28 05:11:44 PM PDT 24
Peak memory 191784 kb
Host smart-93857fc0-fde7-4528-a500-3bb0dabb15d0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3198064760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3198064760
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1314596591
Short name T930
Test name
Test status
Simulation time 71452572 ps
CPU time 0.95 seconds
Started Jul 28 05:11:39 PM PDT 24
Finished Jul 28 05:11:40 PM PDT 24
Peak memory 191812 kb
Host smart-63bb5534-ff89-488c-9a07-4bcf20d76f55
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314596591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1314596591
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3787453007
Short name T919
Test name
Test status
Simulation time 149229525 ps
CPU time 1.24 seconds
Started Jul 28 05:12:00 PM PDT 24
Finished Jul 28 05:12:01 PM PDT 24
Peak memory 198196 kb
Host smart-00cf8e4d-5326-4921-ab3c-bb4d46483537
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3787453007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3787453007
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3442300716
Short name T896
Test name
Test status
Simulation time 19698350 ps
CPU time 0.69 seconds
Started Jul 28 05:11:40 PM PDT 24
Finished Jul 28 05:11:41 PM PDT 24
Peak memory 191596 kb
Host smart-a986a3dd-e1ee-403a-b3ca-a1abad67d51e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442300716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3442300716
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1050178363
Short name T929
Test name
Test status
Simulation time 71692151 ps
CPU time 0.99 seconds
Started Jul 28 05:11:50 PM PDT 24
Finished Jul 28 05:11:51 PM PDT 24
Peak memory 191720 kb
Host smart-6f851fb1-c25a-45c9-9ead-f852a6cc9c9d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1050178363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1050178363
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3685336497
Short name T915
Test name
Test status
Simulation time 101397270 ps
CPU time 0.85 seconds
Started Jul 28 05:11:48 PM PDT 24
Finished Jul 28 05:11:49 PM PDT 24
Peak memory 197984 kb
Host smart-937e5df2-6569-40a9-9e44-20c117852b8b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685336497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3685336497
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1223734567
Short name T893
Test name
Test status
Simulation time 34788185 ps
CPU time 1.11 seconds
Started Jul 28 05:12:09 PM PDT 24
Finished Jul 28 05:12:10 PM PDT 24
Peak memory 191724 kb
Host smart-f94339d5-f7ce-4a27-8da7-550b3e773220
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1223734567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1223734567
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1026158207
Short name T901
Test name
Test status
Simulation time 284240257 ps
CPU time 0.81 seconds
Started Jul 28 05:12:09 PM PDT 24
Finished Jul 28 05:12:10 PM PDT 24
Peak memory 191392 kb
Host smart-b7c6ffd6-a667-4959-8126-0724cd2301d5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026158207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1026158207
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3498218393
Short name T845
Test name
Test status
Simulation time 80987053 ps
CPU time 0.96 seconds
Started Jul 28 05:11:53 PM PDT 24
Finished Jul 28 05:11:54 PM PDT 24
Peak memory 197312 kb
Host smart-e024d2ae-6845-422c-9ce1-6464d2c16760
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3498218393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.3498218393
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1313698707
Short name T914
Test name
Test status
Simulation time 48038910 ps
CPU time 1.3 seconds
Started Jul 28 05:12:06 PM PDT 24
Finished Jul 28 05:12:07 PM PDT 24
Peak memory 197964 kb
Host smart-0d25419c-47e7-4f96-96f9-a48fb7ceabea
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313698707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1313698707
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2490971327
Short name T921
Test name
Test status
Simulation time 139112392 ps
CPU time 1.09 seconds
Started Jul 28 05:11:51 PM PDT 24
Finished Jul 28 05:11:53 PM PDT 24
Peak memory 191720 kb
Host smart-18d53951-4a63-4f16-aba4-5896e60b6f6a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2490971327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2490971327
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2179803461
Short name T942
Test name
Test status
Simulation time 59054553 ps
CPU time 1.18 seconds
Started Jul 28 05:11:48 PM PDT 24
Finished Jul 28 05:11:49 PM PDT 24
Peak memory 198112 kb
Host smart-c220f8bb-cf29-45f4-9b8c-34ba8a254991
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179803461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2179803461
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3240101607
Short name T861
Test name
Test status
Simulation time 52724633 ps
CPU time 1.06 seconds
Started Jul 28 05:11:29 PM PDT 24
Finished Jul 28 05:11:30 PM PDT 24
Peak memory 191776 kb
Host smart-5c0228ce-345c-49c3-829d-d108e5619d4d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3240101607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.3240101607
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3338078332
Short name T922
Test name
Test status
Simulation time 51122833 ps
CPU time 1.12 seconds
Started Jul 28 05:11:39 PM PDT 24
Finished Jul 28 05:11:40 PM PDT 24
Peak memory 197376 kb
Host smart-b6dc56b3-cc0a-4739-86c9-5d460538dc3a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338078332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3338078332
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2767077756
Short name T849
Test name
Test status
Simulation time 37149922 ps
CPU time 0.94 seconds
Started Jul 28 05:11:41 PM PDT 24
Finished Jul 28 05:11:42 PM PDT 24
Peak memory 191784 kb
Host smart-132a1f75-7b68-477e-aa2a-6f6f5b58a474
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2767077756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2767077756
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.180934885
Short name T863
Test name
Test status
Simulation time 100077833 ps
CPU time 1.08 seconds
Started Jul 28 05:11:51 PM PDT 24
Finished Jul 28 05:11:52 PM PDT 24
Peak memory 191720 kb
Host smart-fa3fe8ce-11a5-422b-a11a-04d27566d148
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180934885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.180934885
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2256399691
Short name T908
Test name
Test status
Simulation time 141022934 ps
CPU time 1.03 seconds
Started Jul 28 05:11:33 PM PDT 24
Finished Jul 28 05:11:34 PM PDT 24
Peak memory 197396 kb
Host smart-90949a57-25df-42ec-a858-419fa53f114b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2256399691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2256399691
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1556013298
Short name T854
Test name
Test status
Simulation time 763474591 ps
CPU time 1.42 seconds
Started Jul 28 05:11:48 PM PDT 24
Finished Jul 28 05:11:49 PM PDT 24
Peak memory 198140 kb
Host smart-d267109a-db65-4c3a-a7ff-bf105b81161a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556013298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1556013298
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.105314531
Short name T924
Test name
Test status
Simulation time 464668523 ps
CPU time 1.45 seconds
Started Jul 28 05:11:46 PM PDT 24
Finished Jul 28 05:11:47 PM PDT 24
Peak memory 198092 kb
Host smart-8e1d0878-0820-471b-b783-ea18c4e53fc8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=105314531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.105314531
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.99263320
Short name T887
Test name
Test status
Simulation time 93285227 ps
CPU time 1.3 seconds
Started Jul 28 05:12:02 PM PDT 24
Finished Jul 28 05:12:03 PM PDT 24
Peak memory 191584 kb
Host smart-a1498116-6e84-4c93-9e93-9e6aff47c6c9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99263320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.99263320
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.802371557
Short name T857
Test name
Test status
Simulation time 454322191 ps
CPU time 1.09 seconds
Started Jul 28 05:11:39 PM PDT 24
Finished Jul 28 05:11:40 PM PDT 24
Peak memory 191832 kb
Host smart-3fea7d99-10dc-4f9d-b26e-ebbd29d0265d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=802371557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.802371557
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1595365365
Short name T898
Test name
Test status
Simulation time 80356710 ps
CPU time 1.41 seconds
Started Jul 28 05:11:55 PM PDT 24
Finished Jul 28 05:11:56 PM PDT 24
Peak memory 191764 kb
Host smart-3f0ad0cb-ee68-44c3-8a02-145125ce1adb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595365365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1595365365
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2159925732
Short name T858
Test name
Test status
Simulation time 44552899 ps
CPU time 1.18 seconds
Started Jul 28 05:12:05 PM PDT 24
Finished Jul 28 05:12:07 PM PDT 24
Peak memory 191612 kb
Host smart-c5225d73-09ce-46ea-adbc-c8528ef71ce1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2159925732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2159925732
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.694527423
Short name T937
Test name
Test status
Simulation time 35751156 ps
CPU time 0.78 seconds
Started Jul 28 05:11:49 PM PDT 24
Finished Jul 28 05:11:50 PM PDT 24
Peak memory 191392 kb
Host smart-cf65ea8c-fc68-4b63-8bb7-6f158fd688df
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694527423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.694527423
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.4243858889
Short name T881
Test name
Test status
Simulation time 689344345 ps
CPU time 1.24 seconds
Started Jul 28 05:11:48 PM PDT 24
Finished Jul 28 05:11:49 PM PDT 24
Peak memory 191840 kb
Host smart-94163ee4-d19d-4bbf-aed3-090640368e43
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4243858889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.4243858889
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2539117705
Short name T905
Test name
Test status
Simulation time 47666519 ps
CPU time 1.27 seconds
Started Jul 28 05:11:51 PM PDT 24
Finished Jul 28 05:11:53 PM PDT 24
Peak memory 191744 kb
Host smart-9cd5639e-bf2a-4ca1-81ef-ff1f6dee76e9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539117705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2539117705
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.968272979
Short name T855
Test name
Test status
Simulation time 48221548 ps
CPU time 0.99 seconds
Started Jul 28 05:11:55 PM PDT 24
Finished Jul 28 05:11:56 PM PDT 24
Peak memory 191816 kb
Host smart-0c888e93-584f-4ac1-8c86-528f50883c01
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=968272979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.968272979
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2479282519
Short name T886
Test name
Test status
Simulation time 276888011 ps
CPU time 0.95 seconds
Started Jul 28 05:11:59 PM PDT 24
Finished Jul 28 05:12:00 PM PDT 24
Peak memory 191532 kb
Host smart-36d15a43-0510-42a1-8ad0-eea51276e3f5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479282519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2479282519
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2073613569
Short name T890
Test name
Test status
Simulation time 39566159 ps
CPU time 1.12 seconds
Started Jul 28 05:11:48 PM PDT 24
Finished Jul 28 05:11:49 PM PDT 24
Peak memory 191752 kb
Host smart-7fce16df-5abb-4b97-b476-2d7d68605584
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2073613569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2073613569
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3864944355
Short name T904
Test name
Test status
Simulation time 337498216 ps
CPU time 1.35 seconds
Started Jul 28 05:11:52 PM PDT 24
Finished Jul 28 05:11:54 PM PDT 24
Peak memory 191848 kb
Host smart-673bf42c-bb1c-4bb6-ba71-ffb32000e12f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864944355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3864944355
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.87826689
Short name T940
Test name
Test status
Simulation time 147441076 ps
CPU time 0.84 seconds
Started Jul 28 05:11:52 PM PDT 24
Finished Jul 28 05:11:53 PM PDT 24
Peak memory 191652 kb
Host smart-eeefe073-22f9-42d1-a4d6-27928a4d4102
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=87826689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.87826689
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.295617205
Short name T910
Test name
Test status
Simulation time 93841067 ps
CPU time 0.87 seconds
Started Jul 28 05:11:42 PM PDT 24
Finished Jul 28 05:11:43 PM PDT 24
Peak memory 191544 kb
Host smart-5dbcbf7a-e93e-4378-8f3b-db847385adb7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295617205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.295617205
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3643434534
Short name T851
Test name
Test status
Simulation time 348269040 ps
CPU time 1.32 seconds
Started Jul 28 05:11:55 PM PDT 24
Finished Jul 28 05:11:57 PM PDT 24
Peak memory 191720 kb
Host smart-75daa1a1-de6a-4561-9e28-3c9b745372ee
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3643434534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3643434534
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.780436126
Short name T931
Test name
Test status
Simulation time 57934885 ps
CPU time 1.37 seconds
Started Jul 28 05:11:45 PM PDT 24
Finished Jul 28 05:11:47 PM PDT 24
Peak memory 198156 kb
Host smart-0da2039d-87b0-4805-8b61-c31e8bc6e1f2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780436126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.780436126
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3913080365
Short name T882
Test name
Test status
Simulation time 34263339 ps
CPU time 0.87 seconds
Started Jul 28 05:11:51 PM PDT 24
Finished Jul 28 05:11:52 PM PDT 24
Peak memory 191552 kb
Host smart-3bea6876-f865-4470-b3f9-43872c32b46a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3913080365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3913080365
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2467395753
Short name T859
Test name
Test status
Simulation time 74145449 ps
CPU time 1.25 seconds
Started Jul 28 05:11:42 PM PDT 24
Finished Jul 28 05:11:44 PM PDT 24
Peak memory 198100 kb
Host smart-9cf94b2f-729b-4771-88e0-f1222fd9fa1e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467395753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2467395753
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1450031066
Short name T866
Test name
Test status
Simulation time 240195922 ps
CPU time 1.18 seconds
Started Jul 28 05:12:06 PM PDT 24
Finished Jul 28 05:12:07 PM PDT 24
Peak memory 191612 kb
Host smart-4e1230f4-c52e-4509-a9b9-0cd80ba893a9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1450031066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1450031066
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2880642574
Short name T872
Test name
Test status
Simulation time 32259309 ps
CPU time 0.88 seconds
Started Jul 28 05:12:05 PM PDT 24
Finished Jul 28 05:12:06 PM PDT 24
Peak memory 191392 kb
Host smart-419c8ce5-1f61-4473-ab77-dd1b430aeba3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880642574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2880642574
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.698690433
Short name T891
Test name
Test status
Simulation time 29451752 ps
CPU time 0.87 seconds
Started Jul 28 05:12:02 PM PDT 24
Finished Jul 28 05:12:03 PM PDT 24
Peak memory 191396 kb
Host smart-c1214b51-9570-4441-9f50-9cc326b9eef0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=698690433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.698690433
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.93637157
Short name T933
Test name
Test status
Simulation time 687250782 ps
CPU time 0.96 seconds
Started Jul 28 05:12:06 PM PDT 24
Finished Jul 28 05:12:07 PM PDT 24
Peak memory 191404 kb
Host smart-5034e1c4-eaf6-4ece-81be-2edfef02c374
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93637157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.93637157
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2717153484
Short name T928
Test name
Test status
Simulation time 480557495 ps
CPU time 1.24 seconds
Started Jul 28 05:11:40 PM PDT 24
Finished Jul 28 05:11:42 PM PDT 24
Peak memory 198104 kb
Host smart-7b7e5f8f-5a37-49ab-9e56-ecb74525d794
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2717153484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.2717153484
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1766200545
Short name T911
Test name
Test status
Simulation time 74963142 ps
CPU time 1.17 seconds
Started Jul 28 05:11:38 PM PDT 24
Finished Jul 28 05:11:39 PM PDT 24
Peak memory 191676 kb
Host smart-a63a773c-e07b-49f4-9d83-a13a6f43cfec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766200545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1766200545
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1768851494
Short name T912
Test name
Test status
Simulation time 48857482 ps
CPU time 0.9 seconds
Started Jul 28 05:11:43 PM PDT 24
Finished Jul 28 05:11:44 PM PDT 24
Peak memory 191580 kb
Host smart-8dd46134-659d-4477-b0f0-4c6c9ee7cc19
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1768851494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1768851494
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.744251208
Short name T899
Test name
Test status
Simulation time 48011986 ps
CPU time 0.96 seconds
Started Jul 28 05:11:54 PM PDT 24
Finished Jul 28 05:11:55 PM PDT 24
Peak memory 191760 kb
Host smart-0eb24a32-d105-470e-8ccf-77a9200a9646
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744251208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.744251208
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1344903168
Short name T876
Test name
Test status
Simulation time 46359130 ps
CPU time 1.27 seconds
Started Jul 28 05:11:57 PM PDT 24
Finished Jul 28 05:11:59 PM PDT 24
Peak memory 191812 kb
Host smart-403e3978-9a2b-453d-b555-1ad9bc5d29d7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1344903168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1344903168
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1709133757
Short name T926
Test name
Test status
Simulation time 60638272 ps
CPU time 1.01 seconds
Started Jul 28 05:11:48 PM PDT 24
Finished Jul 28 05:11:49 PM PDT 24
Peak memory 191792 kb
Host smart-574eb3b2-30df-4598-acd1-ee372cd9df1c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709133757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1709133757
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2605934869
Short name T869
Test name
Test status
Simulation time 173833734 ps
CPU time 1.38 seconds
Started Jul 28 05:11:52 PM PDT 24
Finished Jul 28 05:11:54 PM PDT 24
Peak memory 191724 kb
Host smart-d10fe65f-5c63-4a13-a6e4-e8d1c3e309df
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2605934869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2605934869
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.463899324
Short name T862
Test name
Test status
Simulation time 143145060 ps
CPU time 1.24 seconds
Started Jul 28 05:11:57 PM PDT 24
Finished Jul 28 05:11:58 PM PDT 24
Peak memory 191760 kb
Host smart-7ccd4263-78aa-429d-ac69-24f5523d93c5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463899324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.463899324
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3438122519
Short name T943
Test name
Test status
Simulation time 37526002 ps
CPU time 0.93 seconds
Started Jul 28 05:11:52 PM PDT 24
Finished Jul 28 05:11:53 PM PDT 24
Peak memory 197984 kb
Host smart-dacc8464-f3a4-4703-9a17-bd15b39f189c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3438122519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3438122519
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.331938369
Short name T892
Test name
Test status
Simulation time 185139259 ps
CPU time 1.03 seconds
Started Jul 28 05:12:04 PM PDT 24
Finished Jul 28 05:12:05 PM PDT 24
Peak memory 197640 kb
Host smart-c0d3caaf-6448-4ad1-b4ab-179de3126d93
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331938369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.331938369
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3393247184
Short name T877
Test name
Test status
Simulation time 215919384 ps
CPU time 1.03 seconds
Started Jul 28 05:12:00 PM PDT 24
Finished Jul 28 05:12:06 PM PDT 24
Peak memory 197500 kb
Host smart-baa461d1-d88a-4ba3-934e-48140e58c5b7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3393247184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.3393247184
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1001328683
Short name T932
Test name
Test status
Simulation time 17277125 ps
CPU time 0.68 seconds
Started Jul 28 05:11:55 PM PDT 24
Finished Jul 28 05:11:56 PM PDT 24
Peak memory 195216 kb
Host smart-e980f4a9-99d1-4981-9760-ff9bc949d33d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001328683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1001328683
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2045995528
Short name T884
Test name
Test status
Simulation time 141332422 ps
CPU time 1.28 seconds
Started Jul 28 05:11:53 PM PDT 24
Finished Jul 28 05:11:54 PM PDT 24
Peak memory 197988 kb
Host smart-36be2917-a93f-4164-94e7-332c65ec8633
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2045995528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2045995528
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3438242531
Short name T847
Test name
Test status
Simulation time 303729933 ps
CPU time 1.31 seconds
Started Jul 28 05:11:55 PM PDT 24
Finished Jul 28 05:11:57 PM PDT 24
Peak memory 191692 kb
Host smart-6e9f4053-9949-4c25-a51d-5246cea7aaac
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438242531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3438242531
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1902932770
Short name T889
Test name
Test status
Simulation time 70225229 ps
CPU time 1.01 seconds
Started Jul 28 05:11:26 PM PDT 24
Finished Jul 28 05:11:28 PM PDT 24
Peak memory 191832 kb
Host smart-310379bd-7bcb-4a19-9e06-d7c5ac6488fc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1902932770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1902932770
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2543022398
Short name T880
Test name
Test status
Simulation time 280759211 ps
CPU time 1.02 seconds
Started Jul 28 05:11:49 PM PDT 24
Finished Jul 28 05:11:50 PM PDT 24
Peak memory 191556 kb
Host smart-a239b627-1e3d-4d23-a51e-b83c95c382b1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543022398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2543022398
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.974119289
Short name T936
Test name
Test status
Simulation time 440876502 ps
CPU time 0.95 seconds
Started Jul 28 05:11:31 PM PDT 24
Finished Jul 28 05:11:33 PM PDT 24
Peak memory 191776 kb
Host smart-066585cf-f275-4f7c-9b76-388c3a62a284
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=974119289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.974119289
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2439759951
Short name T864
Test name
Test status
Simulation time 63381887 ps
CPU time 1.18 seconds
Started Jul 28 05:11:50 PM PDT 24
Finished Jul 28 05:11:51 PM PDT 24
Peak memory 191828 kb
Host smart-cfbf1e7f-0c08-4c23-b212-312b866c5dd3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439759951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2439759951
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2142904782
Short name T874
Test name
Test status
Simulation time 88498070 ps
CPU time 1.19 seconds
Started Jul 28 05:11:37 PM PDT 24
Finished Jul 28 05:11:38 PM PDT 24
Peak memory 191788 kb
Host smart-4e2338cd-1f85-48f8-80b6-6790b1fa09ea
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2142904782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.2142904782
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3805831501
Short name T883
Test name
Test status
Simulation time 38620742 ps
CPU time 0.79 seconds
Started Jul 28 05:11:42 PM PDT 24
Finished Jul 28 05:11:43 PM PDT 24
Peak memory 191412 kb
Host smart-b43c97fc-dee8-4eaa-a4c4-fda8351322cc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805831501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3805831501
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3839825536
Short name T860
Test name
Test status
Simulation time 85181826 ps
CPU time 1.17 seconds
Started Jul 28 05:12:06 PM PDT 24
Finished Jul 28 05:12:08 PM PDT 24
Peak memory 191760 kb
Host smart-b0f54cce-a746-48a4-92ce-0993e3cb71d5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3839825536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3839825536
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1630126218
Short name T935
Test name
Test status
Simulation time 143600168 ps
CPU time 1.04 seconds
Started Jul 28 05:11:40 PM PDT 24
Finished Jul 28 05:11:41 PM PDT 24
Peak memory 197348 kb
Host smart-f7147b47-5554-4b46-9cff-6f91c43be075
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630126218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1630126218
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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