Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4443842	1			T33	95		T34	1		T1	76
all_pins[1]	4443842	1			T33	95		T34	1		T1	76
all_pins[2]	4443842	1			T33	95		T34	1		T1	76
all_pins[3]	4443842	1			T33	95		T34	1		T1	76
all_pins[4]	4443842	1			T33	95		T34	1		T1	76
all_pins[5]	4443842	1			T33	95		T34	1		T1	76
all_pins[6]	4443842	1			T33	95		T34	1		T1	76
all_pins[7]	4443842	1			T33	95		T34	1		T1	76
all_pins[8]	4443842	1			T33	95		T34	1		T1	76
all_pins[9]	4443842	1			T33	95		T34	1		T1	76
all_pins[10]	4443842	1			T33	95		T34	1		T1	76
all_pins[11]	4443842	1			T33	95		T34	1		T1	76
all_pins[12]	4443842	1			T33	95		T34	1		T1	76
all_pins[13]	4443842	1			T33	95		T34	1		T1	76
all_pins[14]	4443842	1			T33	95		T34	1		T1	76
all_pins[15]	4443842	1			T33	95		T34	1		T1	76
all_pins[16]	4443842	1			T33	95		T34	1		T1	76
all_pins[17]	4443842	1			T33	95		T34	1		T1	76
all_pins[18]	4443842	1			T33	95		T34	1		T1	76
all_pins[19]	4443842	1			T33	95		T34	1		T1	76
all_pins[20]	4443842	1			T33	95		T34	1		T1	76
all_pins[21]	4443842	1			T33	95		T34	1		T1	76
all_pins[22]	4443842	1			T33	95		T34	1		T1	76
all_pins[23]	4443842	1			T33	95		T34	1		T1	76
all_pins[24]	4443842	1			T33	95		T34	1		T1	76
all_pins[25]	4443842	1			T33	95		T34	1		T1	76
all_pins[26]	4443842	1			T33	95		T34	1		T1	76
all_pins[27]	4443842	1			T33	95		T34	1		T1	76
all_pins[28]	4443842	1			T33	95		T34	1		T1	76
all_pins[29]	4443842	1			T33	95		T34	1		T1	76
all_pins[30]	4443842	1			T33	95		T34	1		T1	76
all_pins[31]	4443842	1			T33	95		T34	1		T1	76

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	88325026	1			T33	1518		T34	32		T1	1860
values[0x1]	53877918	1			T33	1522		T1	572		T11	262182
transitions[0x0=>0x1]	32277870	1			T33	740		T1	386		T11	155609
transitions[0x1=>0x0]	32277721	1			T33	740		T1	386		T11	155609

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2761014	1			T33	48		T34	1		T1	53
all_pins[0]	values[0x1]	1682828	1			T33	47		T1	23		T11	8362
all_pins[0]	transitions[0x0=>0x1]	1039429	1			T33	19		T1	13		T11	5114
all_pins[0]	transitions[0x1=>0x0]	1046586	1			T33	23		T1	13		T11	4979
all_pins[1]	values[0x0]	2757959	1			T33	51		T34	1		T1	47
all_pins[1]	values[0x1]	1685883	1			T33	44		T1	29		T11	8380
all_pins[1]	transitions[0x0=>0x1]	1008928	1			T33	20		T1	17		T11	4913
all_pins[1]	transitions[0x1=>0x0]	1005873	1			T33	23		T1	11		T11	4895
all_pins[2]	values[0x0]	2762257	1			T33	55		T34	1		T1	61
all_pins[2]	values[0x1]	1681585	1			T33	40		T1	15		T11	7998
all_pins[2]	transitions[0x0=>0x1]	1005250	1			T33	19		T1	10		T11	4699
all_pins[2]	transitions[0x1=>0x0]	1009548	1			T33	23		T1	24		T11	5081
all_pins[3]	values[0x0]	2760866	1			T33	42		T34	1		T1	62
all_pins[3]	values[0x1]	1682976	1			T33	53		T1	14		T11	8221
all_pins[3]	transitions[0x0=>0x1]	1006809	1			T33	29		T1	11		T11	5054
all_pins[3]	transitions[0x1=>0x0]	1005418	1			T33	16		T1	12		T11	4831
all_pins[4]	values[0x0]	2763391	1			T33	44		T34	1		T1	51
all_pins[4]	values[0x1]	1680451	1			T33	51		T1	25		T11	8222
all_pins[4]	transitions[0x0=>0x1]	1005431	1			T33	19		T1	16		T11	4998
all_pins[4]	transitions[0x1=>0x0]	1007956	1			T33	21		T1	5		T11	4997
all_pins[5]	values[0x0]	2756400	1			T33	43		T34	1		T1	62
all_pins[5]	values[0x1]	1687442	1			T33	52		T1	14		T11	8623
all_pins[5]	transitions[0x0=>0x1]	1010204	1			T33	24		T1	5		T11	5129
all_pins[5]	transitions[0x1=>0x0]	1003213	1			T33	23		T1	16		T11	4728
all_pins[6]	values[0x0]	2762029	1			T33	45		T34	1		T1	60
all_pins[6]	values[0x1]	1681813	1			T33	50		T1	16		T11	8384
all_pins[6]	transitions[0x0=>0x1]	1006149	1			T33	25		T1	11		T11	4878
all_pins[6]	transitions[0x1=>0x0]	1011778	1			T33	27		T1	9		T11	5117
all_pins[7]	values[0x0]	2757478	1			T33	46		T34	1		T1	67
all_pins[7]	values[0x1]	1686364	1			T33	49		T1	9		T11	8118
all_pins[7]	transitions[0x0=>0x1]	1010316	1			T33	24		T1	6		T11	4793
all_pins[7]	transitions[0x1=>0x0]	1005765	1			T33	25		T1	13		T11	5059
all_pins[8]	values[0x0]	2762627	1			T33	54		T34	1		T1	54
all_pins[8]	values[0x1]	1681215	1			T33	41		T1	22		T11	7895
all_pins[8]	transitions[0x0=>0x1]	1004503	1			T33	23		T1	20		T11	4538
all_pins[8]	transitions[0x1=>0x0]	1009652	1			T33	31		T1	7		T11	4761
all_pins[9]	values[0x0]	2760611	1			T33	48		T34	1		T1	64
all_pins[9]	values[0x1]	1683231	1			T33	47		T1	12		T11	8389
all_pins[9]	transitions[0x0=>0x1]	1008550	1			T33	24		T1	11		T11	5116
all_pins[9]	transitions[0x1=>0x0]	1006534	1			T33	18		T1	21		T11	4622
all_pins[10]	values[0x0]	2761748	1			T33	42		T34	1		T1	49
all_pins[10]	values[0x1]	1682094	1			T33	53		T1	27		T11	8248
all_pins[10]	transitions[0x0=>0x1]	1008633	1			T33	27		T1	23		T11	4610
all_pins[10]	transitions[0x1=>0x0]	1009770	1			T33	21		T1	8		T11	4751
all_pins[11]	values[0x0]	2760869	1			T33	49		T34	1		T1	59
all_pins[11]	values[0x1]	1682973	1			T33	46		T1	17		T11	7874
all_pins[11]	transitions[0x0=>0x1]	1007327	1			T33	18		T1	6		T11	4640
all_pins[11]	transitions[0x1=>0x0]	1006448	1			T33	25		T1	16		T11	5014
all_pins[12]	values[0x0]	2764735	1			T33	39		T34	1		T1	65
all_pins[12]	values[0x1]	1679107	1			T33	56		T1	11		T11	8113
all_pins[12]	transitions[0x0=>0x1]	1005264	1			T33	26		T1	7		T11	5048
all_pins[12]	transitions[0x1=>0x0]	1009130	1			T33	16		T1	13		T11	4809
all_pins[13]	values[0x0]	2757706	1			T33	42		T34	1		T1	61
all_pins[13]	values[0x1]	1686136	1			T33	53		T1	15		T11	8168
all_pins[13]	transitions[0x0=>0x1]	1012653	1			T33	20		T1	9		T11	4754
all_pins[13]	transitions[0x1=>0x0]	1005624	1			T33	23		T1	5		T11	4699
all_pins[14]	values[0x0]	2762778	1			T33	52		T34	1		T1	49
all_pins[14]	values[0x1]	1681064	1			T33	43		T1	27		T11	8069
all_pins[14]	transitions[0x0=>0x1]	1004597	1			T33	18		T1	19		T11	4915
all_pins[14]	transitions[0x1=>0x0]	1009669	1			T33	28		T1	7		T11	5014
all_pins[15]	values[0x0]	2758337	1			T33	52		T34	1		T1	66
all_pins[15]	values[0x1]	1685505	1			T33	43		T1	10		T11	8271
all_pins[15]	transitions[0x0=>0x1]	1008590	1			T33	23		T1	6		T11	4943
all_pins[15]	transitions[0x1=>0x0]	1004149	1			T33	23		T1	23		T11	4741
all_pins[16]	values[0x0]	2760692	1			T33	50		T34	1		T1	52
all_pins[16]	values[0x1]	1683150	1			T33	45		T1	24		T11	7767
all_pins[16]	transitions[0x0=>0x1]	1005999	1			T33	25		T1	21		T11	4494
all_pins[16]	transitions[0x1=>0x0]	1008354	1			T33	23		T1	7		T11	4998
all_pins[17]	values[0x0]	2759061	1			T33	51		T34	1		T1	61
all_pins[17]	values[0x1]	1684781	1			T33	44		T1	15		T11	8128
all_pins[17]	transitions[0x0=>0x1]	1007886	1			T33	25		T1	9		T11	4791
all_pins[17]	transitions[0x1=>0x0]	1006255	1			T33	26		T1	18		T11	4430
all_pins[18]	values[0x0]	2763511	1			T33	45		T34	1		T1	53
all_pins[18]	values[0x1]	1680331	1			T33	50		T1	23		T11	8270
all_pins[18]	transitions[0x0=>0x1]	1005202	1			T33	28		T1	19		T11	4930
all_pins[18]	transitions[0x1=>0x0]	1009652	1			T33	22		T1	11		T11	4788
all_pins[19]	values[0x0]	2759945	1			T33	56		T34	1		T1	55
all_pins[19]	values[0x1]	1683897	1			T33	39		T1	21		T11	8051
all_pins[19]	transitions[0x0=>0x1]	1008631	1			T33	19		T1	14		T11	4863
all_pins[19]	transitions[0x1=>0x0]	1005065	1			T33	30		T1	16		T11	5082
all_pins[20]	values[0x0]	2758593	1			T33	50		T34	1		T1	60
all_pins[20]	values[0x1]	1685249	1			T33	45		T1	16		T11	8353
all_pins[20]	transitions[0x0=>0x1]	1007146	1			T33	22		T1	8		T11	4920
all_pins[20]	transitions[0x1=>0x0]	1005794	1			T33	16		T1	13		T11	4618
all_pins[21]	values[0x0]	2760103	1			T33	49		T34	1		T1	56
all_pins[21]	values[0x1]	1683739	1			T33	46		T1	20		T11	8290
all_pins[21]	transitions[0x0=>0x1]	1006630	1			T33	19		T1	13		T11	4892
all_pins[21]	transitions[0x1=>0x0]	1008140	1			T33	18		T1	9		T11	4955
all_pins[22]	values[0x0]	2760456	1			T33	51		T34	1		T1	67
all_pins[22]	values[0x1]	1683386	1			T33	44		T1	9		T11	8121
all_pins[22]	transitions[0x0=>0x1]	1006361	1			T33	23		T1	5		T11	4782
all_pins[22]	transitions[0x1=>0x0]	1006714	1			T33	25		T1	16		T11	4951
all_pins[23]	values[0x0]	2761999	1			T33	55		T34	1		T1	64
all_pins[23]	values[0x1]	1681843	1			T33	40		T1	12		T11	8158
all_pins[23]	transitions[0x0=>0x1]	1007394	1			T33	22		T1	10		T11	4897
all_pins[23]	transitions[0x1=>0x0]	1008937	1			T33	26		T1	7		T11	4860
all_pins[24]	values[0x0]	2757804	1			T33	44		T34	1		T1	67
all_pins[24]	values[0x1]	1686038	1			T33	51		T1	9		T11	8454
all_pins[24]	transitions[0x0=>0x1]	1009184	1			T33	28		T1	5		T11	4977
all_pins[24]	transitions[0x1=>0x0]	1004989	1			T33	17		T1	8		T11	4681
all_pins[25]	values[0x0]	2752960	1			T33	41		T34	1		T1	62
all_pins[25]	values[0x1]	1690882	1			T33	54		T1	14		T11	7887
all_pins[25]	transitions[0x0=>0x1]	1011733	1			T33	29		T1	13		T11	4610
all_pins[25]	transitions[0x1=>0x0]	1006889	1			T33	26		T1	8		T11	5177
all_pins[26]	values[0x0]	2762576	1			T33	51		T34	1		T1	48
all_pins[26]	values[0x1]	1681266	1			T33	44		T1	28		T11	8391
all_pins[26]	transitions[0x0=>0x1]	1005495	1			T33	20		T1	22		T11	5004
all_pins[26]	transitions[0x1=>0x0]	1015111	1			T33	30		T1	8		T11	4500
all_pins[27]	values[0x0]	2763198	1			T33	44		T34	1		T1	61
all_pins[27]	values[0x1]	1680644	1			T33	51		T1	15		T11	7829
all_pins[27]	transitions[0x0=>0x1]	1007149	1			T33	27		T1	6		T11	4593
all_pins[27]	transitions[0x1=>0x0]	1007771	1			T33	20		T1	19		T11	5155
all_pins[28]	values[0x0]	2761725	1			T33	49		T34	1		T1	44
all_pins[28]	values[0x1]	1682117	1			T33	46		T1	32		T11	8109
all_pins[28]	transitions[0x0=>0x1]	1009276	1			T33	18		T1	26		T11	5068
all_pins[28]	transitions[0x1=>0x0]	1007803	1			T33	23		T1	9		T11	4788
all_pins[29]	values[0x0]	2759211	1			T33	40		T34	1		T1	67
all_pins[29]	values[0x1]	1684631	1			T33	55		T1	9		T11	8430
all_pins[29]	transitions[0x0=>0x1]	1008455	1			T33	31		T1	2		T11	4976
all_pins[29]	transitions[0x1=>0x0]	1005941	1			T33	22		T1	25		T11	4655
all_pins[30]	values[0x0]	2758679	1			T33	46		T34	1		T1	60
all_pins[30]	values[0x1]	1685163	1			T33	49		T1	16		T11	8382
all_pins[30]	transitions[0x0=>0x1]	1008011	1			T33	22		T1	12		T11	4870
all_pins[30]	transitions[0x1=>0x0]	1007479	1			T33	28		T1	5		T11	4918
all_pins[31]	values[0x0]	2753708	1			T33	44		T34	1		T1	53
all_pins[31]	values[0x1]	1690134	1			T33	51		T1	23		T11	8227
all_pins[31]	transitions[0x0=>0x1]	1010685	1			T33	24		T1	11		T11	4800
all_pins[31]	transitions[0x1=>0x0]	1005714	1			T33	22		T1	4		T11	4955