Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14789718	1			T33	1496		T34	232		T1	147
all_values[1]	14789718	1			T33	1496		T34	232		T1	147
all_values[2]	14789718	1			T33	1496		T34	232		T1	147
all_values[3]	14789718	1			T33	1496		T34	232		T1	147
all_values[4]	14789718	1			T33	1496		T34	232		T1	147
all_values[5]	14789718	1			T33	1496		T34	232		T1	147
all_values[6]	14789718	1			T33	1496		T34	232		T1	147
all_values[7]	14789718	1			T33	1496		T34	232		T1	147
all_values[8]	14789718	1			T33	1496		T34	232		T1	147
all_values[9]	14789718	1			T33	1496		T34	232		T1	147
all_values[10]	14789718	1			T33	1496		T34	232		T1	147
all_values[11]	14789718	1			T33	1496		T34	232		T1	147
all_values[12]	14789718	1			T33	1496		T34	232		T1	147
all_values[13]	14789718	1			T33	1496		T34	232		T1	147
all_values[14]	14789718	1			T33	1496		T34	232		T1	147
all_values[15]	14789718	1			T33	1496		T34	232		T1	147
all_values[16]	14789718	1			T33	1496		T34	232		T1	147
all_values[17]	14789718	1			T33	1496		T34	232		T1	147
all_values[18]	14789718	1			T33	1496		T34	232		T1	147
all_values[19]	14789718	1			T33	1496		T34	232		T1	147
all_values[20]	14789718	1			T33	1496		T34	232		T1	147
all_values[21]	14789718	1			T33	1496		T34	232		T1	147
all_values[22]	14789718	1			T33	1496		T34	232		T1	147
all_values[23]	14789718	1			T33	1496		T34	232		T1	147
all_values[24]	14789718	1			T33	1496		T34	232		T1	147
all_values[25]	14789718	1			T33	1496		T34	232		T1	147
all_values[26]	14789718	1			T33	1496		T34	232		T1	147
all_values[27]	14789718	1			T33	1496		T34	232		T1	147
all_values[28]	14789718	1			T33	1496		T34	232		T1	147
all_values[29]	14789718	1			T33	1496		T34	232		T1	147
all_values[30]	14789718	1			T33	1496		T34	232		T1	147
all_values[31]	14789718	1			T33	1496		T34	232		T1	147

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

270327644

1

T33

47872

T34

7424

T1

3180

auto[1]

202943332

1

T1

1524

T11

100404

T12

13203

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105983149

1

T33

47872

T34

7424

T1

2464

auto[1]

367287827

1

T1

2240

T11

181835

T12

25100

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

468034101

1

T33

47872

T34

7424

T1

4497

auto[1]

5236875

1

T1

207

T11

13847

T2

231

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2699138	1			T33	1496		T34	232		T1	42
all_values[0]	auto[0]	auto[0]	auto[1]	5697864	1			T1	48		T11	27640		T12	155
all_values[0]	auto[0]	auto[1]	auto[0]	616652	1			T1	18		T11	3246		T12	51
all_values[0]	auto[0]	auto[1]	auto[1]	5612323	1			T1	29		T11	28394		T12	644
all_values[0]	auto[1]	auto[0]	auto[1]	82097	1			T1	7		T11	202		T2	5
all_values[0]	auto[1]	auto[1]	auto[1]	81644	1			T1	3		T11	231		T2	5
all_values[1]	auto[0]	auto[0]	auto[0]	2693128	1			T33	1496		T34	232		T1	47
all_values[1]	auto[0]	auto[0]	auto[1]	5682743	1			T1	34		T11	28694		T12	260
all_values[1]	auto[0]	auto[1]	auto[0]	612885	1			T1	20		T11	2695		T12	57
all_values[1]	auto[0]	auto[1]	auto[1]	5637231	1			T1	41		T11	28374		T12	524
all_values[1]	auto[1]	auto[0]	auto[1]	81832	1			T1	4		T11	214		T2	9
all_values[1]	auto[1]	auto[1]	auto[1]	81899	1			T1	1		T11	213		T2	1
all_values[2]	auto[0]	auto[0]	auto[0]	2699928	1			T33	1496		T34	232		T1	40
all_values[2]	auto[0]	auto[0]	auto[1]	5653269	1			T1	64		T11	28038		T12	315
all_values[2]	auto[0]	auto[1]	auto[0]	620968	1			T1	16		T11	3003		T12	61
all_values[2]	auto[0]	auto[1]	auto[1]	5652167	1			T1	22		T11	28081		T12	441
all_values[2]	auto[1]	auto[0]	auto[1]	82025	1			T1	4		T11	231		T2	10
all_values[2]	auto[1]	auto[1]	auto[1]	81361	1			T1	1		T11	192		T2	2
all_values[3]	auto[0]	auto[0]	auto[0]	2712675	1			T33	1496		T34	232		T1	63
all_values[3]	auto[0]	auto[0]	auto[1]	5671917	1			T1	23		T11	27129		T12	285
all_values[3]	auto[0]	auto[1]	auto[0]	604832	1			T1	41		T11	2494		T12	21
all_values[3]	auto[0]	auto[1]	auto[1]	5636977	1			T1	17		T11	29491		T12	511
all_values[3]	auto[1]	auto[0]	auto[1]	81964	1			T1	1		T11	232		T2	4
all_values[3]	auto[1]	auto[1]	auto[1]	81353	1			T1	2		T11	207		T2	1
all_values[4]	auto[0]	auto[0]	auto[0]	2698227	1			T33	1496		T34	232		T1	41
all_values[4]	auto[0]	auto[0]	auto[1]	5673498	1			T1	35		T11	28436		T12	437
all_values[4]	auto[0]	auto[1]	auto[0]	617666	1			T1	26		T11	2981		T12	50
all_values[4]	auto[0]	auto[1]	auto[1]	5636479	1			T1	36		T11	28017		T12	326
all_values[4]	auto[1]	auto[0]	auto[1]	81907	1			T1	7		T11	225		T2	4
all_values[4]	auto[1]	auto[1]	auto[1]	81941	1			T1	2		T11	216		T2	2
all_values[5]	auto[0]	auto[0]	auto[0]	2699667	1			T33	1496		T34	232		T1	60
all_values[5]	auto[0]	auto[0]	auto[1]	5640529	1			T1	30		T11	25944		T12	539
all_values[5]	auto[0]	auto[1]	auto[0]	608689	1			T1	29		T11	3111		T12	22
all_values[5]	auto[0]	auto[1]	auto[1]	5676965	1			T1	22		T11	30326		T12	171
all_values[5]	auto[1]	auto[0]	auto[1]	82094	1			T1	5		T11	191		T2	6
all_values[5]	auto[1]	auto[1]	auto[1]	81774	1			T1	1		T11	226		T17	721
all_values[6]	auto[0]	auto[0]	auto[0]	2710874	1			T33	1496		T34	232		T1	51
all_values[6]	auto[0]	auto[0]	auto[1]	5667736	1			T1	33		T11	28438		T12	379
all_values[6]	auto[0]	auto[1]	auto[0]	610230	1			T1	40		T11	2446		T12	56
all_values[6]	auto[0]	auto[1]	auto[1]	5637051	1			T1	18		T11	28404		T12	365
all_values[6]	auto[1]	auto[0]	auto[1]	81678	1			T1	2		T11	184		T2	5
all_values[6]	auto[1]	auto[1]	auto[1]	82149	1			T1	3		T11	269		T2	1
all_values[7]	auto[0]	auto[0]	auto[0]	2698966	1			T33	1496		T34	232		T1	76
all_values[7]	auto[0]	auto[0]	auto[1]	5622980	1			T1	39		T11	28144		T12	309
all_values[7]	auto[0]	auto[1]	auto[0]	611029	1			T1	12		T11	3104		T12	19
all_values[7]	auto[0]	auto[1]	auto[1]	5692774	1			T1	14		T11	27780		T12	496
all_values[7]	auto[1]	auto[0]	auto[1]	82529	1			T1	6		T11	213		T2	7
all_values[7]	auto[1]	auto[1]	auto[1]	81440	1			T11	227		T2	1		T17	733
all_values[8]	auto[0]	auto[0]	auto[0]	2699311	1			T33	1496		T34	232		T1	45
all_values[8]	auto[0]	auto[0]	auto[1]	5671005	1			T1	44		T11	29163		T12	350
all_values[8]	auto[0]	auto[1]	auto[0]	612759	1			T1	22		T11	2866		T12	18
all_values[8]	auto[0]	auto[1]	auto[1]	5642420	1			T1	30		T11	26813		T12	477
all_values[8]	auto[1]	auto[0]	auto[1]	81919	1			T1	3		T11	229		T2	3
all_values[8]	auto[1]	auto[1]	auto[1]	82304	1			T1	3		T11	186		T2	3
all_values[9]	auto[0]	auto[0]	auto[0]	2710101	1			T33	1496		T34	232		T1	62
all_values[9]	auto[0]	auto[0]	auto[1]	5682991	1			T1	38		T11	27997		T12	420
all_values[9]	auto[0]	auto[1]	auto[0]	605729	1			T1	22		T11	2535		T12	16
all_values[9]	auto[0]	auto[1]	auto[1]	5626758	1			T1	19		T11	28869		T12	394
all_values[9]	auto[1]	auto[0]	auto[1]	82091	1			T1	5		T11	200		T2	5
all_values[9]	auto[1]	auto[1]	auto[1]	82048	1			T1	1		T11	237		T2	4
all_values[10]	auto[0]	auto[0]	auto[0]	2709003	1			T33	1496		T34	232		T1	62
all_values[10]	auto[0]	auto[0]	auto[1]	5649659	1			T1	34		T11	28296		T12	340
all_values[10]	auto[0]	auto[1]	auto[0]	607894	1			T1	10		T11	2674		T12	32
all_values[10]	auto[0]	auto[1]	auto[1]	5659505	1			T1	36		T11	28531		T12	474
all_values[10]	auto[1]	auto[0]	auto[1]	82314	1			T1	1		T11	206		T2	7
all_values[10]	auto[1]	auto[1]	auto[1]	81343	1			T1	4		T11	254		T2	2
all_values[11]	auto[0]	auto[0]	auto[0]	2700210	1			T33	1496		T34	232		T1	64
all_values[11]	auto[0]	auto[0]	auto[1]	5685521	1			T1	42		T11	30181		T12	382
all_values[11]	auto[0]	auto[1]	auto[0]	600912	1			T1	10		T11	3046		T12	36
all_values[11]	auto[0]	auto[1]	auto[1]	5639076	1			T1	24		T11	26429		T12	419
all_values[11]	auto[1]	auto[0]	auto[1]	82315	1			T1	5		T11	229		T2	4
all_values[11]	auto[1]	auto[1]	auto[1]	81684	1			T1	2		T11	205		T2	1
all_values[12]	auto[0]	auto[0]	auto[0]	2706560	1			T33	1496		T34	232		T1	78
all_values[12]	auto[0]	auto[0]	auto[1]	5680351	1			T1	27		T11	28412		T12	252
all_values[12]	auto[0]	auto[1]	auto[0]	611667	1			T1	19		T11	3161		T12	43
all_values[12]	auto[0]	auto[1]	auto[1]	5627577	1			T1	16		T11	27876		T12	543
all_values[12]	auto[1]	auto[0]	auto[1]	82351	1			T1	5		T11	214		T2	3
all_values[12]	auto[1]	auto[1]	auto[1]	81212	1			T1	2		T11	208		T2	2
all_values[13]	auto[0]	auto[0]	auto[0]	2703780	1			T33	1496		T34	232		T1	60
all_values[13]	auto[0]	auto[0]	auto[1]	5651873	1			T1	53		T11	27815		T12	492
all_values[13]	auto[0]	auto[1]	auto[0]	602698	1			T1	10		T11	2800		T12	39
all_values[13]	auto[0]	auto[1]	auto[1]	5667500	1			T1	21		T11	28897		T12	279
all_values[13]	auto[1]	auto[0]	auto[1]	81729	1			T1	3		T11	200		T2	2
all_values[13]	auto[1]	auto[1]	auto[1]	82138	1			T11	228		T2	6		T17	772
all_values[14]	auto[0]	auto[0]	auto[0]	2699143	1			T33	1496		T34	232		T1	54
all_values[14]	auto[0]	auto[0]	auto[1]	5657828	1			T1	36		T11	28756		T12	485
all_values[14]	auto[0]	auto[1]	auto[0]	617021	1			T1	18		T11	2765		T12	18
all_values[14]	auto[0]	auto[1]	auto[1]	5651832	1			T1	34		T11	27941		T12	297
all_values[14]	auto[1]	auto[0]	auto[1]	82170	1			T1	2		T11	221		T2	7
all_values[14]	auto[1]	auto[1]	auto[1]	81724	1			T1	3		T11	212		T2	1
all_values[15]	auto[0]	auto[0]	auto[0]	2693776	1			T33	1496		T34	232		T1	58
all_values[15]	auto[0]	auto[0]	auto[1]	5670784	1			T1	55		T11	27166		T12	420
all_values[15]	auto[0]	auto[1]	auto[0]	611209	1			T1	15		T11	3057		T12	12
all_values[15]	auto[0]	auto[1]	auto[1]	5650267	1			T1	12		T11	29426		T12	376
all_values[15]	auto[1]	auto[0]	auto[1]	81928	1			T1	5		T11	202		T2	9
all_values[15]	auto[1]	auto[1]	auto[1]	81754	1			T1	2		T11	208		T2	1
all_values[16]	auto[0]	auto[0]	auto[0]	2696948	1			T33	1496		T34	232		T1	53
all_values[16]	auto[0]	auto[0]	auto[1]	5655884	1			T1	29		T11	28467		T12	626
all_values[16]	auto[0]	auto[1]	auto[0]	605074	1			T1	25		T11	2731		T12	22
all_values[16]	auto[0]	auto[1]	auto[1]	5668409	1			T1	32		T11	27908		T12	178
all_values[16]	auto[1]	auto[0]	auto[1]	82478	1			T1	3		T11	216		T2	2
all_values[16]	auto[1]	auto[1]	auto[1]	80925	1			T1	5		T11	214		T2	4
all_values[17]	auto[0]	auto[0]	auto[0]	2700794	1			T33	1496		T34	232		T1	50
all_values[17]	auto[0]	auto[0]	auto[1]	5608011	1			T1	57		T11	27916		T12	465
all_values[17]	auto[0]	auto[1]	auto[0]	613815	1			T1	12		T11	2865		T12	18
all_values[17]	auto[0]	auto[1]	auto[1]	5703182	1			T1	24		T11	28786		T12	273
all_values[17]	auto[1]	auto[0]	auto[1]	82188	1			T1	3		T11	220		T2	8
all_values[17]	auto[1]	auto[1]	auto[1]	81728	1			T1	1		T11	202		T17	739
all_values[18]	auto[0]	auto[0]	auto[0]	2711303	1			T33	1496		T34	232		T1	60
all_values[18]	auto[0]	auto[0]	auto[1]	5643764	1			T1	30		T11	27831		T12	441
all_values[18]	auto[0]	auto[1]	auto[0]	606859	1			T1	15		T11	3444		T12	29
all_values[18]	auto[0]	auto[1]	auto[1]	5664544	1			T1	35		T11	27648		T12	372
all_values[18]	auto[1]	auto[0]	auto[1]	82081	1			T1	5		T11	227		T2	5
all_values[18]	auto[1]	auto[1]	auto[1]	81167	1			T1	2		T11	188		T2	3
all_values[19]	auto[0]	auto[0]	auto[0]	2706825	1			T33	1496		T34	232		T1	58
all_values[19]	auto[0]	auto[0]	auto[1]	5658269	1			T1	25		T11	28216		T12	492
all_values[19]	auto[0]	auto[1]	auto[0]	597391	1			T1	29		T11	2547		T12	46
all_values[19]	auto[0]	auto[1]	auto[1]	5663777	1			T1	29		T11	28442		T12	295
all_values[19]	auto[1]	auto[0]	auto[1]	81698	1			T1	4		T11	235		T2	5
all_values[19]	auto[1]	auto[1]	auto[1]	81758	1			T1	2		T11	180		T2	3
all_values[20]	auto[0]	auto[0]	auto[0]	2703149	1			T33	1496		T34	232		T1	59
all_values[20]	auto[0]	auto[0]	auto[1]	5650847	1			T1	39		T11	27354		T12	642
all_values[20]	auto[0]	auto[1]	auto[0]	606629	1			T1	16		T11	3518		T12	1
all_values[20]	auto[0]	auto[1]	auto[1]	5665677	1			T1	24		T11	28656		T12	191
all_values[20]	auto[1]	auto[0]	auto[1]	81735	1			T1	6		T11	233		T2	7
all_values[20]	auto[1]	auto[1]	auto[1]	81681	1			T1	3		T11	215		T2	1
all_values[21]	auto[0]	auto[0]	auto[0]	2700837	1			T33	1496		T34	232		T1	42
all_values[21]	auto[0]	auto[0]	auto[1]	5693149	1			T1	49		T11	28122		T12	560
all_values[21]	auto[0]	auto[1]	auto[0]	613970	1			T1	24		T11	2838		T12	20
all_values[21]	auto[0]	auto[1]	auto[1]	5617905	1			T1	26		T11	28472		T12	223
all_values[21]	auto[1]	auto[0]	auto[1]	82237	1			T1	2		T11	194		T2	4
all_values[21]	auto[1]	auto[1]	auto[1]	81620	1			T1	4		T11	228		T2	3
all_values[22]	auto[0]	auto[0]	auto[0]	2704930	1			T33	1496		T34	232		T1	52
all_values[22]	auto[0]	auto[0]	auto[1]	5643181	1			T1	53		T11	28099		T12	303
all_values[22]	auto[0]	auto[1]	auto[0]	613704	1			T1	22		T11	2956		T12	19
all_values[22]	auto[0]	auto[1]	auto[1]	5664732	1			T1	12		T11	27961		T12	486
all_values[22]	auto[1]	auto[0]	auto[1]	81914	1			T1	7		T11	213		T2	7
all_values[22]	auto[1]	auto[1]	auto[1]	81257	1			T1	1		T11	214		T2	1
all_values[23]	auto[0]	auto[0]	auto[0]	2705753	1			T33	1496		T34	232		T1	66
all_values[23]	auto[0]	auto[0]	auto[1]	5663351	1			T1	38		T11	27627		T12	296
all_values[23]	auto[0]	auto[1]	auto[0]	611000	1			T1	19		T11	3085		T12	43
all_values[23]	auto[0]	auto[1]	auto[1]	5646271	1			T1	17		T11	28100		T12	511
all_values[23]	auto[1]	auto[0]	auto[1]	81856	1			T1	5		T11	221		T2	4
all_values[23]	auto[1]	auto[1]	auto[1]	81487	1			T1	2		T11	217		T17	753
all_values[24]	auto[0]	auto[0]	auto[0]	2700147	1			T33	1496		T34	232		T1	71
all_values[24]	auto[0]	auto[0]	auto[1]	5678417	1			T1	28		T11	27650		T12	253
all_values[24]	auto[0]	auto[1]	auto[0]	610795	1			T1	27		T11	2918		T12	95
all_values[24]	auto[0]	auto[1]	auto[1]	5636821	1			T1	13		T11	28875		T12	483
all_values[24]	auto[1]	auto[0]	auto[1]	82221	1			T1	8		T11	237		T2	3
all_values[24]	auto[1]	auto[1]	auto[1]	81317	1			T11	206		T2	6		T17	699
all_values[25]	auto[0]	auto[0]	auto[0]	2692533	1			T33	1496		T34	232		T1	51
all_values[25]	auto[0]	auto[0]	auto[1]	5693437	1			T1	45		T11	30616		T12	333
all_values[25]	auto[0]	auto[1]	auto[0]	604302	1			T1	26		T11	2508		T12	26
all_values[25]	auto[0]	auto[1]	auto[1]	5635778	1			T1	19		T11	26351		T12	484
all_values[25]	auto[1]	auto[0]	auto[1]	82122	1			T1	3		T11	225		T2	9
all_values[25]	auto[1]	auto[1]	auto[1]	81546	1			T1	3		T11	198		T2	3
all_values[26]	auto[0]	auto[0]	auto[0]	2701727	1			T33	1496		T34	232		T1	45
all_values[26]	auto[0]	auto[0]	auto[1]	5672743	1			T1	32		T11	28572		T12	262
all_values[26]	auto[0]	auto[1]	auto[0]	608593	1			T1	30		T11	2778		T12	25
all_values[26]	auto[0]	auto[1]	auto[1]	5643378	1			T1	32		T11	28281		T12	538
all_values[26]	auto[1]	auto[0]	auto[1]	82162	1			T1	2		T11	222		T2	4
all_values[26]	auto[1]	auto[1]	auto[1]	81115	1			T1	6		T11	223		T2	1
all_values[27]	auto[0]	auto[0]	auto[0]	2703965	1			T33	1496		T34	232		T1	58
all_values[27]	auto[0]	auto[0]	auto[1]	5675701	1			T1	42		T11	28757		T12	594
all_values[27]	auto[0]	auto[1]	auto[0]	609551	1			T1	14		T11	2890		T12	6
all_values[27]	auto[0]	auto[1]	auto[1]	5636732	1			T1	26		T11	26973		T12	155
all_values[27]	auto[1]	auto[0]	auto[1]	82164	1			T1	5		T11	203		T2	1
all_values[27]	auto[1]	auto[1]	auto[1]	81605	1			T1	2		T11	221		T2	2
all_values[28]	auto[0]	auto[0]	auto[0]	2694767	1			T33	1496		T34	232		T1	43
all_values[28]	auto[0]	auto[0]	auto[1]	5667549	1			T1	35		T11	28330		T12	544
all_values[28]	auto[0]	auto[1]	auto[0]	610835	1			T1	17		T11	3234		T12	19
all_values[28]	auto[0]	auto[1]	auto[1]	5652907	1			T1	43		T11	27755		T12	199
all_values[28]	auto[1]	auto[0]	auto[1]	81460	1			T1	4		T11	237		T2	7
all_values[28]	auto[1]	auto[1]	auto[1]	82200	1			T1	5		T11	216		T2	2
all_values[29]	auto[0]	auto[0]	auto[0]	2704065	1			T33	1496		T34	232		T1	75
all_values[29]	auto[0]	auto[0]	auto[1]	5687612	1			T1	27		T11	27236		T12	258
all_values[29]	auto[0]	auto[1]	auto[0]	608513	1			T1	27		T11	2911		T12	46
all_values[29]	auto[0]	auto[1]	auto[1]	5626336	1			T1	15		T11	29208		T12	499
all_values[29]	auto[1]	auto[0]	auto[1]	81611	1			T1	2		T11	202		T2	2
all_values[29]	auto[1]	auto[1]	auto[1]	81581	1			T1	1		T11	235		T17	738
all_values[30]	auto[0]	auto[0]	auto[0]	2694369	1			T33	1496		T34	232		T1	48
all_values[30]	auto[0]	auto[0]	auto[1]	5662885	1			T1	52		T11	28343		T12	469
all_values[30]	auto[0]	auto[1]	auto[0]	609120	1			T1	17		T11	2823		T12	47
all_values[30]	auto[0]	auto[1]	auto[1]	5659535	1			T1	22		T11	28415		T12	310
all_values[30]	auto[1]	auto[0]	auto[1]	81557	1			T1	6		T11	246		T2	5
all_values[30]	auto[1]	auto[1]	auto[1]	82252	1			T1	2		T11	188		T17	761
all_values[31]	auto[0]	auto[0]	auto[0]	2705001	1			T33	1496		T34	232		T1	66
all_values[31]	auto[0]	auto[0]	auto[1]	5626584	1			T1	30		T11	27136		T12	564
all_values[31]	auto[0]	auto[1]	auto[0]	618558	1			T1	16		T11	3103		T12	12
all_values[31]	auto[0]	auto[1]	auto[1]	5676134	1			T1	27		T11	28510		T12	244
all_values[31]	auto[1]	auto[0]	auto[1]	81685	1			T1	4		T11	205		T2	1
all_values[31]	auto[1]	auto[1]	auto[1]	81756	1			T1	4		T11	254		T2	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal