Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[1]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[2]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[3]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[4]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[5]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[6]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[7]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[8]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[9]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[10]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[11]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[12]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[13]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[14]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[15]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[16]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[17]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[18]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[19]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[20]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[21]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[22]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[23]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[24]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[25]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[26]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[27]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[28]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[29]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[30]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[31]	14596083	1			T33	1496		T34	451		T1	166

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

278776819

1

T33

23967

T34

3069

T1

2610

auto[1]

188297837

1

T33

23905

T34

11363

T1

2702

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

373376357

1

T33

47872

T34

10539

T1

4791

auto[1]

93698299

1

T34

3893

T1

521

T11

422048

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

345447906

1

T33

47872

T34

7677

T1

3865

auto[1]

121626750

1

T34

6755

T1

1447

T11

572146

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5376286	1			T33	700		T34	22		T1	58
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3944483	1			T33	796		T34	130		T1	43
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1471866	1			T34	82		T11	6708		T13	172
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1864941	1			T34	19		T1	42		T11	10640
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	478516	1			T34	135		T1	17		T11	930
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1459991	1			T34	63		T1	6		T11	6651
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5366439	1			T33	755		T34	16		T1	33
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3954691	1			T33	741		T34	165		T1	65
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1474395	1			T34	46		T1	2		T11	6574
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1863301	1			T34	19		T1	18		T11	10753
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	477815	1			T34	131		T1	15		T11	931
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1459442	1			T34	74		T1	33		T11	6503
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5378868	1			T33	670		T34	18		T1	62
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3947156	1			T33	826		T34	123		T1	35
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1469257	1			T34	72		T1	9		T11	6701
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1860754	1			T34	10		T1	28		T11	10560
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	477570	1			T34	163		T1	11		T11	948
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1462478	1			T34	65		T1	21		T11	6720
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5372359	1			T33	662		T34	20		T1	69
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3954566	1			T33	834		T34	187		T1	59
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1469733	1			T34	91		T1	12		T11	6375
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1858895	1			T34	12		T1	8		T11	10353
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	476308	1			T34	111		T1	12		T11	889
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1464222	1			T34	30		T1	6		T11	7101
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5388717	1			T33	820		T34	21		T1	99
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3934439	1			T33	676		T34	173		T1	44
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1476203	1			T34	75		T1	4		T11	6439
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1856835	1			T34	7		T1	16		T11	11051
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	479917	1			T34	151		T1	3		T11	994
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1459972	1			T34	24		T11	6472		T13	202
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5379200	1			T33	704		T34	20		T1	37
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3942430	1			T33	792		T34	180		T1	46
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1470976	1			T34	36		T11	6641		T13	217
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1863879	1			T34	15		T1	35		T11	10607
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	478510	1			T34	122		T1	23		T11	903
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1461088	1			T34	78		T1	25		T11	6462
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5379260	1			T33	755		T34	20		T1	37
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3941366	1			T33	741		T34	244		T1	100
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1473341	1			T34	51		T11	6450		T13	171
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1861496	1			T34	11		T1	8		T11	10251
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	480315	1			T34	79		T1	16		T11	838
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1460305	1			T34	46		T1	5		T11	6826
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5377466	1			T33	737		T34	21		T1	41
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3941912	1			T33	759		T34	184		T1	91
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1471927	1			T34	69		T1	6		T11	6644
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1864569	1			T34	15		T1	16		T11	10689
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	479496	1			T34	113		T1	9		T11	857
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1460713	1			T34	49		T1	3		T11	6603
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5369590	1			T33	764		T34	14		T1	42
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3958534	1			T33	732		T34	126		T1	53
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1472118	1			T34	77		T11	6657		T13	185
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1859463	1			T34	19		T1	17		T11	10336
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	476297	1			T34	167		T1	17		T11	848
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1460081	1			T34	48		T1	37		T11	6439
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5385038	1			T33	748		T34	30		T1	63
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3945660	1			T33	748		T34	213		T1	85
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1473985	1			T34	35		T11	6507		T13	173
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1858558	1			T34	11		T1	4		T11	11099
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	476712	1			T34	124		T1	8		T11	910
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1456130	1			T34	38		T1	6		T11	6297
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5376311	1			T33	703		T34	24		T1	40
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3944052	1			T33	793		T34	140		T1	68
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1471549	1			T34	84		T1	6		T11	6400
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1863064	1			T34	14		T1	15		T11	10307
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	482805	1			T34	114		T1	17		T11	861
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1458302	1			T34	75		T1	20		T11	6701
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5367794	1			T33	754		T34	19		T1	41
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3949508	1			T33	742		T34	129		T1	64
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1477426	1			T34	38		T11	7170		T13	187
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1863224	1			T34	15		T1	12		T11	9798
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	481397	1			T34	150		T1	24		T11	854
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1456734	1			T34	100		T1	25		T11	6651
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5366126	1			T33	795		T34	22		T1	50
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3955518	1			T33	701		T34	159		T1	34
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1477165	1			T34	49		T1	1		T11	6455
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1859330	1			T34	20		T1	31		T11	10299
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	476519	1			T34	138		T1	31		T11	829
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1461425	1			T34	63		T1	19		T11	6515
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5385615	1			T33	767		T34	22		T1	60
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3940216	1			T33	729		T34	160		T1	56
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1473563	1			T34	83		T11	6394		T13	173
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1859778	1			T34	13		T1	28		T11	10722
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	478073	1			T34	129		T1	8		T11	937
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1458838	1			T34	44		T1	14		T11	6374
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5365661	1			T33	729		T34	30		T1	54
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3953505	1			T33	767		T34	174		T1	52
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1470262	1			T34	76		T11	6700		T13	212
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1864846	1			T34	12		T1	16		T11	9881
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	481464	1			T34	120		T1	26		T11	820
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1460345	1			T34	39		T1	18		T11	6258
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5375244	1			T33	845		T34	10		T1	79
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3949106	1			T33	651		T34	162		T1	35
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1471331	1			T34	30		T1	17		T11	6590
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1866211	1			T34	12		T1	22		T11	10603
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	478550	1			T34	140		T1	4		T11	898
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1455641	1			T34	97		T1	9		T11	6621
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5379373	1			T33	757		T34	17		T1	61
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3946869	1			T33	739		T34	116		T1	60
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1470007	1			T34	50		T1	13		T11	6790
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1864288	1			T34	28		T1	21		T11	10268
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	480472	1			T34	152		T1	7		T11	852
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1455074	1			T34	88		T1	4		T11	6884
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5366932	1			T33	765		T34	22		T1	67
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3955804	1			T33	731		T34	194		T1	53
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1468879	1			T34	81		T1	1		T11	6539
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1864920	1			T34	12		T1	9		T11	10276
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	478831	1			T34	89		T1	29		T11	884
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1460717	1			T34	53		T1	7		T11	6758
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5366839	1			T33	754		T34	10		T1	52
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3956918	1			T33	742		T34	112		T1	64
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1471633	1			T34	50		T1	7		T11	6602
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1866295	1			T34	28		T1	5		T11	10235
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	477478	1			T34	170		T1	27		T11	835
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1456920	1			T34	81		T1	11		T11	6758
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5362950	1			T33	797		T34	25		T1	120
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3959812	1			T33	699		T34	165		T1	25
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1467578	1			T34	51		T1	7		T11	6569
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1869047	1			T34	14		T1	14		T11	10581
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	480636	1			T34	131		T11	935		T2	10
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1456060	1			T34	65		T11	6280		T13	192
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5395031	1			T33	758		T34	19		T1	65
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3935854	1			T33	738		T34	125		T1	58
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1467946	1			T34	52		T1	15		T11	6500
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1864102	1			T34	13		T1	23		T11	10544
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	480830	1			T34	176		T1	5		T11	941
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1452320	1			T34	66		T11	6554		T13	182
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5384561	1			T33	725		T34	13		T1	62
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3948154	1			T33	771		T34	120		T1	39
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1469298	1			T34	74		T11	6322		T13	202
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1862772	1			T34	19		T1	35		T11	10297
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	478150	1			T34	170		T1	19		T11	843
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1453148	1			T34	55		T1	11		T11	6855
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5372095	1			T33	668		T34	26		T1	37
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3955181	1			T33	828		T34	190		T1	103
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1465710	1			T34	72		T1	3		T11	6596
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1866046	1			T34	10		T1	14		T11	10471
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	481363	1			T34	105		T1	6		T11	924
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1455688	1			T34	48		T1	3		T11	6542
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5381011	1			T33	838		T34	29		T1	28
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3945257	1			T33	658		T34	188		T1	87
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1463665	1			T34	58		T1	13		T11	6897
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1869405	1			T34	15		T1	6		T11	9882
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	480540	1			T34	113		T1	21		T11	797
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1456205	1			T34	48		T1	11		T11	6660
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5384364	1			T33	790		T34	11		T1	64
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3943803	1			T33	706		T34	137		T1	59
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1457424	1			T34	49		T1	5		T11	6637
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1871619	1			T34	15		T1	13		T11	10546
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	479213	1			T34	147		T1	10		T11	910
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1459660	1			T34	92		T1	15		T11	6457
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5386318	1			T33	736		T34	8		T1	51
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3936983	1			T33	760		T34	95		T1	53
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1469100	1			T34	30		T1	14		T11	6869
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1867282	1			T34	33		T1	20		T11	10450
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	481322	1			T34	153		T1	16		T11	788
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1455078	1			T34	132		T1	12		T11	6468
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5379491	1			T33	733		T34	31		T1	84
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3944561	1			T33	763		T34	202		T1	29
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1467498	1			T34	80		T1	1		T11	6528
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1867580	1			T34	11		T1	36		T11	10547
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	482101	1			T34	89		T1	12		T11	835
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1454852	1			T34	38		T1	4		T11	6630
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5386167	1			T33	735		T34	22		T1	55
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3944637	1			T33	761		T34	110		T1	50
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1467128	1			T34	25		T1	16		T11	6785
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1865770	1			T34	22		T1	24		T11	10163
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	478283	1			T34	187		T1	12		T11	853
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1454098	1			T34	85		T1	9		T11	6487
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5380749	1			T33	773		T34	21		T1	76
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3946915	1			T33	723		T34	226		T1	45
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1469753	1			T34	84		T1	2		T11	6933
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1863558	1			T34	12		T1	34		T11	10104
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	479492	1			T34	80		T1	8		T11	815
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1455616	1			T34	28		T1	1		T11	6234
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5390694	1			T33	691		T34	14		T1	53
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3939967	1			T33	805		T34	214		T1	63
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1471825	1			T34	49		T1	8		T11	6597
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1857863	1			T34	18		T1	26		T11	10439
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	480033	1			T34	93		T1	11		T11	898
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1455701	1			T34	63		T1	5		T11	6253
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5380094	1			T33	805		T34	17		T1	55
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3948583	1			T33	691		T34	121		T1	81
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1473712	1			T34	69		T1	1		T11	6669
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1859734	1			T34	19		T1	12		T11	10425
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	478799	1			T34	182		T1	9		T11	854
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1455161	1			T34	43		T1	8		T11	6549
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5381494	1			T33	734		T34	20		T1	24
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3942976	1			T33	762		T34	153		T1	83
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1464100	1			T34	58		T1	1		T11	6570
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1868904	1			T34	16		T1	19		T11	10604
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	482668	1			T34	155		T1	30		T11	914
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1455941	1			T34	49		T1	9		T11	6677

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal