Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[1]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[2]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[3]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[4]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[5]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[6]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[7]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[8]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[9]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[10]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[11]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[12]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[13]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[14]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[15]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[16]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[17]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[18]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[19]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[20]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[21]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[22]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[23]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[24]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[25]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[26]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[27]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[28]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[29]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[30]	14596083	1			T33	1496		T34	451		T1	166
bins_for_gpio_bits[31]	14596083	1			T33	1496		T34	451		T1	166

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

278776819

1

T33

23967

T34

3069

T1

2610

auto[1]

188297837

1

T33

23905

T34

11363

T1

2702

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

278768649

1

T33

23967

T34

3077

T1

2614

auto[1]

188306007

1

T33

23905

T34

11355

T1

2698

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	8451303	1			T33	700		T34	112		T1	100
bins_for_gpio_bits[0]	auto[0]	auto[1]	261525	1			T34	11		T11	1338		T13	44
bins_for_gpio_bits[0]	auto[1]	auto[0]	261790	1			T34	11		T11	1348		T13	44
bins_for_gpio_bits[0]	auto[1]	auto[1]	5621465	1			T33	796		T34	317		T1	66
bins_for_gpio_bits[1]	auto[0]	auto[0]	8442784	1			T33	755		T34	72		T1	52
bins_for_gpio_bits[1]	auto[0]	auto[1]	261077	1			T34	10		T11	1350		T13	48
bins_for_gpio_bits[1]	auto[1]	auto[0]	261351	1			T34	9		T1	1		T11	1360
bins_for_gpio_bits[1]	auto[1]	auto[1]	5630871	1			T33	741		T34	360		T1	113
bins_for_gpio_bits[2]	auto[0]	auto[0]	8447565	1			T33	670		T34	91		T1	99
bins_for_gpio_bits[2]	auto[0]	auto[1]	261070	1			T34	10		T11	1366		T13	53
bins_for_gpio_bits[2]	auto[1]	auto[0]	261314	1			T34	9		T11	1371		T13	54
bins_for_gpio_bits[2]	auto[1]	auto[1]	5626134	1			T33	826		T34	341		T1	67
bins_for_gpio_bits[3]	auto[0]	auto[0]	8439759	1			T33	662		T34	112		T1	89
bins_for_gpio_bits[3]	auto[0]	auto[1]	260988	1			T34	11		T11	1381		T13	39
bins_for_gpio_bits[3]	auto[1]	auto[0]	261228	1			T34	11		T11	1384		T13	40
bins_for_gpio_bits[3]	auto[1]	auto[1]	5634108	1			T33	834		T34	317		T1	77
bins_for_gpio_bits[4]	auto[0]	auto[0]	8460768	1			T33	820		T34	93		T1	119
bins_for_gpio_bits[4]	auto[0]	auto[1]	260735	1			T34	10		T11	1320		T13	46
bins_for_gpio_bits[4]	auto[1]	auto[0]	260987	1			T34	10		T11	1323		T13	46
bins_for_gpio_bits[4]	auto[1]	auto[1]	5613593	1			T33	676		T34	338		T1	47
bins_for_gpio_bits[5]	auto[0]	auto[0]	8452889	1			T33	704		T34	66		T1	71
bins_for_gpio_bits[5]	auto[0]	auto[1]	260936	1			T34	6		T1	1		T11	1355
bins_for_gpio_bits[5]	auto[1]	auto[0]	261166	1			T34	5		T1	1		T11	1360
bins_for_gpio_bits[5]	auto[1]	auto[1]	5621092	1			T33	792		T34	374		T1	93
bins_for_gpio_bits[6]	auto[0]	auto[0]	8452811	1			T33	755		T34	74		T1	45
bins_for_gpio_bits[6]	auto[0]	auto[1]	261028	1			T34	8		T11	1339		T13	43
bins_for_gpio_bits[6]	auto[1]	auto[0]	261286	1			T34	8		T11	1342		T13	43
bins_for_gpio_bits[6]	auto[1]	auto[1]	5620958	1			T33	741		T34	361		T1	121
bins_for_gpio_bits[7]	auto[0]	auto[0]	8452362	1			T33	737		T34	91		T1	63
bins_for_gpio_bits[7]	auto[0]	auto[1]	261366	1			T34	15		T11	1354		T13	45
bins_for_gpio_bits[7]	auto[1]	auto[0]	261600	1			T34	14		T11	1360		T13	45
bins_for_gpio_bits[7]	auto[1]	auto[1]	5620755	1			T33	759		T34	331		T1	103
bins_for_gpio_bits[8]	auto[0]	auto[0]	8439846	1			T33	764		T34	98		T1	59
bins_for_gpio_bits[8]	auto[0]	auto[1]	261092	1			T34	12		T11	1331		T13	46
bins_for_gpio_bits[8]	auto[1]	auto[0]	261325	1			T34	12		T11	1339		T13	46
bins_for_gpio_bits[8]	auto[1]	auto[1]	5633820	1			T33	732		T34	329		T1	107
bins_for_gpio_bits[9]	auto[0]	auto[0]	8456392	1			T33	748		T34	70		T1	67
bins_for_gpio_bits[9]	auto[0]	auto[1]	260910	1			T34	6		T11	1331		T13	47
bins_for_gpio_bits[9]	auto[1]	auto[0]	261189	1			T34	6		T11	1333		T13	47
bins_for_gpio_bits[9]	auto[1]	auto[1]	5617592	1			T33	748		T34	369		T1	99
bins_for_gpio_bits[10]	auto[0]	auto[0]	8450029	1			T33	703		T34	112		T1	61
bins_for_gpio_bits[10]	auto[0]	auto[1]	260599	1			T34	10		T1	1		T11	1324
bins_for_gpio_bits[10]	auto[1]	auto[0]	260895	1			T34	10		T11	1332		T13	48
bins_for_gpio_bits[10]	auto[1]	auto[1]	5624560	1			T33	793		T34	319		T1	104
bins_for_gpio_bits[11]	auto[0]	auto[0]	8447533	1			T33	754		T34	66		T1	53
bins_for_gpio_bits[11]	auto[0]	auto[1]	260648	1			T34	6		T11	1344		T13	54
bins_for_gpio_bits[11]	auto[1]	auto[0]	260911	1			T34	6		T11	1351		T13	54
bins_for_gpio_bits[11]	auto[1]	auto[1]	5626991	1			T33	742		T34	373		T1	113
bins_for_gpio_bits[12]	auto[0]	auto[0]	8441166	1			T33	795		T34	82		T1	82
bins_for_gpio_bits[12]	auto[0]	auto[1]	261193	1			T34	9		T1	1		T11	1323
bins_for_gpio_bits[12]	auto[1]	auto[0]	261455	1			T34	9		T11	1327		T13	53
bins_for_gpio_bits[12]	auto[1]	auto[1]	5632269	1			T33	701		T34	351		T1	83
bins_for_gpio_bits[13]	auto[0]	auto[0]	8457614	1			T33	767		T34	104		T1	88
bins_for_gpio_bits[13]	auto[0]	auto[1]	261087	1			T34	15		T11	1344		T13	48
bins_for_gpio_bits[13]	auto[1]	auto[0]	261342	1			T34	14		T11	1349		T13	48
bins_for_gpio_bits[13]	auto[1]	auto[1]	5616040	1			T33	729		T34	318		T1	78
bins_for_gpio_bits[14]	auto[0]	auto[0]	8439667	1			T33	729		T34	109		T1	70
bins_for_gpio_bits[14]	auto[0]	auto[1]	260846	1			T34	9		T11	1273		T13	46
bins_for_gpio_bits[14]	auto[1]	auto[0]	261102	1			T34	9		T11	1278		T13	47
bins_for_gpio_bits[14]	auto[1]	auto[1]	5634468	1			T33	767		T34	324		T1	96
bins_for_gpio_bits[15]	auto[0]	auto[0]	8451998	1			T33	845		T34	44		T1	118
bins_for_gpio_bits[15]	auto[0]	auto[1]	260508	1			T34	8		T1	1		T11	1345
bins_for_gpio_bits[15]	auto[1]	auto[0]	260788	1			T34	8		T11	1351		T13	44
bins_for_gpio_bits[15]	auto[1]	auto[1]	5622789	1			T33	651		T34	391		T1	47
bins_for_gpio_bits[16]	auto[0]	auto[0]	8452440	1			T33	757		T34	89		T1	95
bins_for_gpio_bits[16]	auto[0]	auto[1]	260963	1			T34	7		T11	1371		T13	47
bins_for_gpio_bits[16]	auto[1]	auto[0]	261228	1			T34	6		T11	1376		T13	47
bins_for_gpio_bits[16]	auto[1]	auto[1]	5621452	1			T33	739		T34	349		T1	71
bins_for_gpio_bits[17]	auto[0]	auto[0]	8439092	1			T33	765		T34	99		T1	77
bins_for_gpio_bits[17]	auto[0]	auto[1]	261391	1			T34	16		T11	1353		T13	41
bins_for_gpio_bits[17]	auto[1]	auto[0]	261639	1			T34	16		T11	1359		T13	41
bins_for_gpio_bits[17]	auto[1]	auto[1]	5633961	1			T33	731		T34	320		T1	89
bins_for_gpio_bits[18]	auto[0]	auto[0]	8442581	1			T33	754		T34	78		T1	64
bins_for_gpio_bits[18]	auto[0]	auto[1]	261970	1			T34	10		T11	1359		T13	47
bins_for_gpio_bits[18]	auto[1]	auto[0]	262186	1			T34	10		T11	1363		T13	48
bins_for_gpio_bits[18]	auto[1]	auto[1]	5629346	1			T33	742		T34	353		T1	102
bins_for_gpio_bits[19]	auto[0]	auto[0]	8437983	1			T33	797		T34	80		T1	141
bins_for_gpio_bits[19]	auto[0]	auto[1]	261389	1			T34	10		T11	1340		T13	54
bins_for_gpio_bits[19]	auto[1]	auto[0]	261592	1			T34	10		T11	1347		T13	54
bins_for_gpio_bits[19]	auto[1]	auto[1]	5635119	1			T33	699		T34	351		T1	25
bins_for_gpio_bits[20]	auto[0]	auto[0]	8466611	1			T33	758		T34	74		T1	103
bins_for_gpio_bits[20]	auto[0]	auto[1]	260227	1			T34	10		T11	1317		T13	50
bins_for_gpio_bits[20]	auto[1]	auto[0]	260468	1			T34	10		T11	1322		T13	50
bins_for_gpio_bits[20]	auto[1]	auto[1]	5608777	1			T33	738		T34	357		T1	63
bins_for_gpio_bits[21]	auto[0]	auto[0]	8455150	1			T33	725		T34	94		T1	97
bins_for_gpio_bits[21]	auto[0]	auto[1]	261182	1			T34	13		T11	1354		T13	44
bins_for_gpio_bits[21]	auto[1]	auto[0]	261481	1			T34	12		T11	1360		T13	44
bins_for_gpio_bits[21]	auto[1]	auto[1]	5618270	1			T33	771		T34	332		T1	69
bins_for_gpio_bits[22]	auto[0]	auto[0]	8442195	1			T33	668		T34	98		T1	54
bins_for_gpio_bits[22]	auto[0]	auto[1]	261384	1			T34	11		T11	1312		T13	54
bins_for_gpio_bits[22]	auto[1]	auto[0]	261656	1			T34	10		T11	1317		T13	54
bins_for_gpio_bits[22]	auto[1]	auto[1]	5630848	1			T33	828		T34	332		T1	112
bins_for_gpio_bits[23]	auto[0]	auto[0]	8452831	1			T33	838		T34	91		T1	47
bins_for_gpio_bits[23]	auto[0]	auto[1]	260998	1			T34	11		T1	1		T11	1338
bins_for_gpio_bits[23]	auto[1]	auto[0]	261250	1			T34	11		T11	1342		T13	46
bins_for_gpio_bits[23]	auto[1]	auto[1]	5621004	1			T33	658		T34	338		T1	118
bins_for_gpio_bits[24]	auto[0]	auto[0]	8452281	1			T33	790		T34	65		T1	82
bins_for_gpio_bits[24]	auto[0]	auto[1]	260895	1			T34	10		T1	1		T11	1325
bins_for_gpio_bits[24]	auto[1]	auto[0]	261126	1			T34	10		T11	1331		T13	40
bins_for_gpio_bits[24]	auto[1]	auto[1]	5621781	1			T33	706		T34	366		T1	83
bins_for_gpio_bits[25]	auto[0]	auto[0]	8461067	1			T33	736		T34	63		T1	85
bins_for_gpio_bits[25]	auto[0]	auto[1]	261339	1			T34	8		T11	1342		T13	43
bins_for_gpio_bits[25]	auto[1]	auto[0]	261633	1			T34	8		T11	1350		T13	44
bins_for_gpio_bits[25]	auto[1]	auto[1]	5612044	1			T33	760		T34	372		T1	81
bins_for_gpio_bits[26]	auto[0]	auto[0]	8452781	1			T33	733		T34	107		T1	121
bins_for_gpio_bits[26]	auto[0]	auto[1]	261530	1			T34	15		T11	1331		T13	55
bins_for_gpio_bits[26]	auto[1]	auto[0]	261788	1			T34	15		T11	1335		T13	55
bins_for_gpio_bits[26]	auto[1]	auto[1]	5619984	1			T33	763		T34	314		T1	45
bins_for_gpio_bits[27]	auto[0]	auto[0]	8457234	1			T33	735		T34	60		T1	95
bins_for_gpio_bits[27]	auto[0]	auto[1]	261567	1			T34	9		T11	1307		T13	45
bins_for_gpio_bits[27]	auto[1]	auto[0]	261831	1			T34	9		T11	1308		T13	45
bins_for_gpio_bits[27]	auto[1]	auto[1]	5615451	1			T33	761		T34	373		T1	71
bins_for_gpio_bits[28]	auto[0]	auto[0]	8452444	1			T33	773		T34	106		T1	112
bins_for_gpio_bits[28]	auto[0]	auto[1]	261356	1			T34	11		T11	1272		T13	46
bins_for_gpio_bits[28]	auto[1]	auto[0]	261616	1			T34	11		T11	1276		T13	47
bins_for_gpio_bits[28]	auto[1]	auto[1]	5620667	1			T33	723		T34	323		T1	54
bins_for_gpio_bits[29]	auto[0]	auto[0]	8458765	1			T33	691		T34	72		T1	87
bins_for_gpio_bits[29]	auto[0]	auto[1]	261372	1			T34	9		T11	1320		T13	44
bins_for_gpio_bits[29]	auto[1]	auto[0]	261617	1			T34	9		T11	1323		T13	44
bins_for_gpio_bits[29]	auto[1]	auto[1]	5614329	1			T33	805		T34	361		T1	79
bins_for_gpio_bits[30]	auto[0]	auto[0]	8451838	1			T33	805		T34	100		T1	68
bins_for_gpio_bits[30]	auto[0]	auto[1]	261443	1			T34	5		T11	1335		T13	43
bins_for_gpio_bits[30]	auto[1]	auto[0]	261702	1			T34	5		T11	1338		T13	43
bins_for_gpio_bits[30]	auto[1]	auto[1]	5621100	1			T33	691		T34	341		T1	98
bins_for_gpio_bits[31]	auto[0]	auto[0]	8452959	1			T33	734		T34	83		T1	44
bins_for_gpio_bits[31]	auto[0]	auto[1]	261297	1			T34	11		T11	1317		T13	50
bins_for_gpio_bits[31]	auto[1]	auto[0]	261539	1			T34	11		T11	1321		T13	50
bins_for_gpio_bits[31]	auto[1]	auto[1]	5620288	1			T33	762		T34	346		T1	122