Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8479099 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
97 |
| auto[1] |
6310619 |
1 |
|
|
T1 |
50 |
|
T11 |
31871 |
|
T12 |
695 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13970892 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
144 |
| auto[1] |
818826 |
1 |
|
|
T1 |
3 |
|
T11 |
4821 |
|
T12 |
75 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8403191 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
110 |
| auto[1] |
6386527 |
1 |
|
|
T1 |
37 |
|
T11 |
30937 |
|
T12 |
415 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2802128 |
1 |
|
|
T1 |
24 |
|
T11 |
13054 |
|
T12 |
40 |
| auto[1] |
auto[0] |
auto[1] |
412828 |
1 |
|
|
T1 |
3 |
|
T11 |
2374 |
|
T12 |
10 |
| auto[1] |
auto[1] |
auto[0] |
2765573 |
1 |
|
|
T1 |
10 |
|
T11 |
13062 |
|
T12 |
300 |
| auto[1] |
auto[1] |
auto[1] |
405998 |
1 |
|
|
T11 |
2447 |
|
T12 |
65 |
|
T17 |
3892 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8457703 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
85 |
| auto[1] |
6332015 |
1 |
|
|
T1 |
62 |
|
T11 |
31282 |
|
T12 |
581 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13976078 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
147 |
| auto[1] |
813640 |
1 |
|
|
T11 |
5003 |
|
T12 |
80 |
|
T17 |
7534 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8446120 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
101 |
| auto[1] |
6343598 |
1 |
|
|
T1 |
46 |
|
T11 |
32229 |
|
T12 |
415 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2757894 |
1 |
|
|
T1 |
26 |
|
T11 |
14309 |
|
T12 |
148 |
| auto[1] |
auto[0] |
auto[1] |
405474 |
1 |
|
|
T11 |
2600 |
|
T12 |
36 |
|
T17 |
3415 |
| auto[1] |
auto[1] |
auto[0] |
2772064 |
1 |
|
|
T1 |
20 |
|
T11 |
12917 |
|
T12 |
187 |
| auto[1] |
auto[1] |
auto[1] |
408166 |
1 |
|
|
T11 |
2403 |
|
T12 |
44 |
|
T17 |
4119 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8440976 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
97 |
| auto[1] |
6348742 |
1 |
|
|
T1 |
50 |
|
T11 |
31459 |
|
T12 |
506 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13980426 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
146 |
| auto[1] |
809292 |
1 |
|
|
T1 |
1 |
|
T11 |
5165 |
|
T12 |
50 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8462028 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
121 |
| auto[1] |
6327690 |
1 |
|
|
T1 |
26 |
|
T11 |
32534 |
|
T12 |
262 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2751030 |
1 |
|
|
T1 |
13 |
|
T11 |
14015 |
|
T12 |
72 |
| auto[1] |
auto[0] |
auto[1] |
402108 |
1 |
|
|
T11 |
2704 |
|
T12 |
18 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2767368 |
1 |
|
|
T1 |
12 |
|
T11 |
13354 |
|
T12 |
140 |
| auto[1] |
auto[1] |
auto[1] |
407184 |
1 |
|
|
T1 |
1 |
|
T11 |
2461 |
|
T12 |
32 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8468046 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
111 |
| auto[1] |
6321672 |
1 |
|
|
T1 |
36 |
|
T11 |
29680 |
|
T12 |
455 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13975051 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
145 |
| auto[1] |
814667 |
1 |
|
|
T1 |
2 |
|
T11 |
5060 |
|
T12 |
76 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8435111 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
82 |
| auto[1] |
6354607 |
1 |
|
|
T1 |
65 |
|
T11 |
31786 |
|
T12 |
378 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2768793 |
1 |
|
|
T1 |
50 |
|
T11 |
14136 |
|
T12 |
180 |
| auto[1] |
auto[0] |
auto[1] |
407416 |
1 |
|
|
T1 |
2 |
|
T11 |
2695 |
|
T12 |
42 |
| auto[1] |
auto[1] |
auto[0] |
2771147 |
1 |
|
|
T1 |
13 |
|
T11 |
12590 |
|
T12 |
122 |
| auto[1] |
auto[1] |
auto[1] |
407251 |
1 |
|
|
T11 |
2365 |
|
T12 |
34 |
|
T17 |
3419 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8469262 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
110 |
| auto[1] |
6320456 |
1 |
|
|
T1 |
37 |
|
T11 |
31245 |
|
T12 |
586 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13980275 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
147 |
| auto[1] |
809443 |
1 |
|
|
T11 |
4961 |
|
T12 |
97 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8467317 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
81 |
| auto[1] |
6322401 |
1 |
|
|
T1 |
66 |
|
T11 |
31892 |
|
T12 |
512 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2760980 |
1 |
|
|
T1 |
50 |
|
T11 |
13743 |
|
T12 |
112 |
| auto[1] |
auto[0] |
auto[1] |
405066 |
1 |
|
|
T11 |
2502 |
|
T12 |
26 |
|
T17 |
3326 |
| auto[1] |
auto[1] |
auto[0] |
2751978 |
1 |
|
|
T1 |
16 |
|
T11 |
13188 |
|
T12 |
303 |
| auto[1] |
auto[1] |
auto[1] |
404377 |
1 |
|
|
T11 |
2459 |
|
T12 |
71 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8437382 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
116 |
| auto[1] |
6352336 |
1 |
|
|
T1 |
31 |
|
T11 |
31925 |
|
T12 |
318 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13976490 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
147 |
| auto[1] |
813228 |
1 |
|
|
T11 |
5188 |
|
T12 |
95 |
|
T17 |
7031 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8434724 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
115 |
| auto[1] |
6354994 |
1 |
|
|
T1 |
32 |
|
T11 |
32525 |
|
T12 |
516 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2761282 |
1 |
|
|
T1 |
28 |
|
T11 |
13796 |
|
T12 |
265 |
| auto[1] |
auto[0] |
auto[1] |
406041 |
1 |
|
|
T11 |
2564 |
|
T12 |
56 |
|
T17 |
3427 |
| auto[1] |
auto[1] |
auto[0] |
2780484 |
1 |
|
|
T1 |
4 |
|
T11 |
13541 |
|
T12 |
156 |
| auto[1] |
auto[1] |
auto[1] |
407187 |
1 |
|
|
T11 |
2624 |
|
T12 |
39 |
|
T17 |
3604 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8439141 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
92 |
| auto[1] |
6350577 |
1 |
|
|
T1 |
55 |
|
T11 |
30918 |
|
T12 |
315 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13977271 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
146 |
| auto[1] |
812447 |
1 |
|
|
T1 |
1 |
|
T11 |
4802 |
|
T12 |
111 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8443428 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
112 |
| auto[1] |
6346290 |
1 |
|
|
T1 |
35 |
|
T11 |
30425 |
|
T12 |
625 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2766818 |
1 |
|
|
T1 |
24 |
|
T11 |
13383 |
|
T12 |
306 |
| auto[1] |
auto[0] |
auto[1] |
406436 |
1 |
|
|
T1 |
1 |
|
T11 |
2494 |
|
T12 |
70 |
| auto[1] |
auto[1] |
auto[0] |
2767025 |
1 |
|
|
T1 |
10 |
|
T11 |
12240 |
|
T12 |
208 |
| auto[1] |
auto[1] |
auto[1] |
406011 |
1 |
|
|
T11 |
2308 |
|
T12 |
41 |
|
T17 |
3569 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8446488 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
118 |
| auto[1] |
6343230 |
1 |
|
|
T1 |
29 |
|
T11 |
32691 |
|
T12 |
388 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13977968 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
145 |
| auto[1] |
811750 |
1 |
|
|
T1 |
2 |
|
T11 |
4904 |
|
T12 |
90 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8450888 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
92 |
| auto[1] |
6338830 |
1 |
|
|
T1 |
55 |
|
T11 |
30780 |
|
T12 |
480 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2762994 |
1 |
|
|
T1 |
47 |
|
T11 |
12744 |
|
T12 |
190 |
| auto[1] |
auto[0] |
auto[1] |
404744 |
1 |
|
|
T1 |
2 |
|
T11 |
2438 |
|
T12 |
46 |
| auto[1] |
auto[1] |
auto[0] |
2764086 |
1 |
|
|
T1 |
6 |
|
T11 |
13132 |
|
T12 |
200 |
| auto[1] |
auto[1] |
auto[1] |
407006 |
1 |
|
|
T11 |
2466 |
|
T12 |
44 |
|
T17 |
3613 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8435310 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
85 |
| auto[1] |
6354408 |
1 |
|
|
T1 |
62 |
|
T11 |
30853 |
|
T12 |
200 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13975092 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
147 |
| auto[1] |
814626 |
1 |
|
|
T11 |
5093 |
|
T12 |
122 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8432013 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
120 |
| auto[1] |
6357705 |
1 |
|
|
T1 |
27 |
|
T11 |
32036 |
|
T12 |
607 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2778059 |
1 |
|
|
T1 |
13 |
|
T11 |
13901 |
|
T12 |
387 |
| auto[1] |
auto[0] |
auto[1] |
408096 |
1 |
|
|
T11 |
2615 |
|
T12 |
101 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2765020 |
1 |
|
|
T1 |
14 |
|
T11 |
13042 |
|
T12 |
98 |
| auto[1] |
auto[1] |
auto[1] |
406530 |
1 |
|
|
T11 |
2478 |
|
T12 |
21 |
|
T17 |
3361 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8390993 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
110 |
| auto[1] |
6398725 |
1 |
|
|
T1 |
37 |
|
T11 |
31853 |
|
T12 |
291 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13974009 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
147 |
| auto[1] |
815709 |
1 |
|
|
T11 |
4753 |
|
T12 |
75 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8432567 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
105 |
| auto[1] |
6357151 |
1 |
|
|
T1 |
42 |
|
T11 |
30259 |
|
T12 |
421 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2756015 |
1 |
|
|
T1 |
23 |
|
T11 |
12729 |
|
T12 |
202 |
| auto[1] |
auto[0] |
auto[1] |
404204 |
1 |
|
|
T11 |
2299 |
|
T12 |
44 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2785427 |
1 |
|
|
T1 |
19 |
|
T11 |
12777 |
|
T12 |
144 |
| auto[1] |
auto[1] |
auto[1] |
411505 |
1 |
|
|
T11 |
2454 |
|
T12 |
31 |
|
T17 |
3960 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8437148 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
95 |
| auto[1] |
6352570 |
1 |
|
|
T1 |
52 |
|
T11 |
31280 |
|
T12 |
401 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13977043 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
147 |
| auto[1] |
812675 |
1 |
|
|
T11 |
4994 |
|
T12 |
84 |
|
T17 |
7264 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8450580 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
102 |
| auto[1] |
6339138 |
1 |
|
|
T1 |
45 |
|
T11 |
31583 |
|
T12 |
428 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2757719 |
1 |
|
|
T1 |
21 |
|
T11 |
13716 |
|
T12 |
248 |
| auto[1] |
auto[0] |
auto[1] |
405649 |
1 |
|
|
T11 |
2574 |
|
T12 |
62 |
|
T17 |
3476 |
| auto[1] |
auto[1] |
auto[0] |
2768744 |
1 |
|
|
T1 |
24 |
|
T11 |
12873 |
|
T12 |
96 |
| auto[1] |
auto[1] |
auto[1] |
407026 |
1 |
|
|
T11 |
2420 |
|
T12 |
22 |
|
T17 |
3788 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8446792 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
87 |
| auto[1] |
6342926 |
1 |
|
|
T1 |
60 |
|
T11 |
31169 |
|
T12 |
341 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13972322 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
145 |
| auto[1] |
817396 |
1 |
|
|
T1 |
2 |
|
T11 |
5030 |
|
T12 |
76 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8431576 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
99 |
| auto[1] |
6358142 |
1 |
|
|
T1 |
48 |
|
T11 |
31427 |
|
T12 |
405 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2777019 |
1 |
|
|
T1 |
16 |
|
T11 |
12862 |
|
T12 |
119 |
| auto[1] |
auto[0] |
auto[1] |
410861 |
1 |
|
|
T1 |
1 |
|
T11 |
2408 |
|
T12 |
30 |
| auto[1] |
auto[1] |
auto[0] |
2763727 |
1 |
|
|
T1 |
30 |
|
T11 |
13535 |
|
T12 |
210 |
| auto[1] |
auto[1] |
auto[1] |
406535 |
1 |
|
|
T1 |
1 |
|
T11 |
2622 |
|
T12 |
46 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8435222 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
108 |
| auto[1] |
6354496 |
1 |
|
|
T1 |
39 |
|
T11 |
31276 |
|
T12 |
502 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13976956 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
147 |
| auto[1] |
812762 |
1 |
|
|
T11 |
4934 |
|
T12 |
63 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8444861 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
124 |
| auto[1] |
6344857 |
1 |
|
|
T1 |
23 |
|
T11 |
31237 |
|
T12 |
361 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2766407 |
1 |
|
|
T1 |
20 |
|
T11 |
13664 |
|
T12 |
146 |
| auto[1] |
auto[0] |
auto[1] |
406583 |
1 |
|
|
T11 |
2569 |
|
T12 |
33 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2765688 |
1 |
|
|
T1 |
3 |
|
T11 |
12639 |
|
T12 |
152 |
| auto[1] |
auto[1] |
auto[1] |
406179 |
1 |
|
|
T11 |
2365 |
|
T12 |
30 |
|
T17 |
3681 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8435731 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
104 |
| auto[1] |
6353987 |
1 |
|
|
T1 |
43 |
|
T11 |
32389 |
|
T12 |
192 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13981138 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
145 |
| auto[1] |
808580 |
1 |
|
|
T1 |
2 |
|
T11 |
5042 |
|
T12 |
54 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8471650 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
121 |
| auto[1] |
6318068 |
1 |
|
|
T1 |
26 |
|
T11 |
32117 |
|
T12 |
257 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2757603 |
1 |
|
|
T1 |
20 |
|
T11 |
13419 |
|
T12 |
137 |
| auto[1] |
auto[0] |
auto[1] |
405504 |
1 |
|
|
T1 |
2 |
|
T11 |
2525 |
|
T12 |
35 |
| auto[1] |
auto[1] |
auto[0] |
2751885 |
1 |
|
|
T1 |
4 |
|
T11 |
13656 |
|
T12 |
66 |
| auto[1] |
auto[1] |
auto[1] |
403076 |
1 |
|
|
T11 |
2517 |
|
T12 |
19 |
|
T17 |
3799 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8476223 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
93 |
| auto[1] |
6313495 |
1 |
|
|
T1 |
54 |
|
T11 |
31538 |
|
T12 |
243 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13981469 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
145 |
| auto[1] |
808249 |
1 |
|
|
T1 |
2 |
|
T11 |
5270 |
|
T12 |
47 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8482546 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
89 |
| auto[1] |
6307172 |
1 |
|
|
T1 |
58 |
|
T11 |
33630 |
|
T12 |
250 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2755762 |
1 |
|
|
T1 |
42 |
|
T11 |
13786 |
|
T12 |
154 |
| auto[1] |
auto[0] |
auto[1] |
404875 |
1 |
|
|
T1 |
2 |
|
T11 |
2565 |
|
T12 |
36 |
| auto[1] |
auto[1] |
auto[0] |
2743161 |
1 |
|
|
T1 |
14 |
|
T11 |
14574 |
|
T12 |
49 |
| auto[1] |
auto[1] |
auto[1] |
403374 |
1 |
|
|
T11 |
2705 |
|
T12 |
11 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8430025 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
112 |
| auto[1] |
6359693 |
1 |
|
|
T1 |
35 |
|
T11 |
31131 |
|
T12 |
505 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13978073 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
147 |
| auto[1] |
811645 |
1 |
|
|
T11 |
4742 |
|
T12 |
121 |
|
T17 |
7043 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8447264 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
107 |
| auto[1] |
6342454 |
1 |
|
|
T1 |
40 |
|
T11 |
30637 |
|
T12 |
615 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2762637 |
1 |
|
|
T1 |
30 |
|
T11 |
12675 |
|
T12 |
217 |
| auto[1] |
auto[0] |
auto[1] |
405106 |
1 |
|
|
T11 |
2317 |
|
T12 |
51 |
|
T17 |
3496 |
| auto[1] |
auto[1] |
auto[0] |
2768172 |
1 |
|
|
T1 |
10 |
|
T11 |
13220 |
|
T12 |
277 |
| auto[1] |
auto[1] |
auto[1] |
406539 |
1 |
|
|
T11 |
2425 |
|
T12 |
70 |
|
T17 |
3547 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8450960 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
109 |
| auto[1] |
6338758 |
1 |
|
|
T1 |
38 |
|
T11 |
31402 |
|
T12 |
554 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13983969 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
146 |
| auto[1] |
805749 |
1 |
|
|
T1 |
1 |
|
T11 |
4746 |
|
T12 |
78 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8485167 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
102 |
| auto[1] |
6304551 |
1 |
|
|
T1 |
45 |
|
T11 |
30519 |
|
T12 |
431 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2766590 |
1 |
|
|
T1 |
28 |
|
T11 |
11926 |
|
T12 |
101 |
| auto[1] |
auto[0] |
auto[1] |
406077 |
1 |
|
|
T1 |
1 |
|
T11 |
2220 |
|
T12 |
23 |
| auto[1] |
auto[1] |
auto[0] |
2732212 |
1 |
|
|
T1 |
16 |
|
T11 |
13847 |
|
T12 |
252 |
| auto[1] |
auto[1] |
auto[1] |
399672 |
1 |
|
|
T11 |
2526 |
|
T12 |
55 |
|
T17 |
3322 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8460785 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
107 |
| auto[1] |
6328933 |
1 |
|
|
T1 |
40 |
|
T11 |
31999 |
|
T12 |
578 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13984745 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
146 |
| auto[1] |
804973 |
1 |
|
|
T1 |
1 |
|
T11 |
5059 |
|
T12 |
69 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8486991 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
106 |
| auto[1] |
6302727 |
1 |
|
|
T1 |
41 |
|
T11 |
31891 |
|
T12 |
355 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2755471 |
1 |
|
|
T1 |
26 |
|
T11 |
13399 |
|
T12 |
57 |
| auto[1] |
auto[0] |
auto[1] |
403308 |
1 |
|
|
T1 |
1 |
|
T11 |
2495 |
|
T12 |
10 |
| auto[1] |
auto[1] |
auto[0] |
2742283 |
1 |
|
|
T1 |
14 |
|
T11 |
13433 |
|
T12 |
229 |
| auto[1] |
auto[1] |
auto[1] |
401665 |
1 |
|
|
T11 |
2564 |
|
T12 |
59 |
|
T17 |
3449 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8468092 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
99 |
| auto[1] |
6321626 |
1 |
|
|
T1 |
48 |
|
T11 |
29057 |
|
T12 |
510 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13973282 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
145 |
| auto[1] |
816436 |
1 |
|
|
T1 |
2 |
|
T11 |
4771 |
|
T12 |
88 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8434244 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
96 |
| auto[1] |
6355474 |
1 |
|
|
T1 |
51 |
|
T11 |
30499 |
|
T12 |
490 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2775059 |
1 |
|
|
T1 |
31 |
|
T11 |
13123 |
|
T12 |
165 |
| auto[1] |
auto[0] |
auto[1] |
408977 |
1 |
|
|
T1 |
2 |
|
T11 |
2450 |
|
T12 |
40 |
| auto[1] |
auto[1] |
auto[0] |
2763979 |
1 |
|
|
T1 |
18 |
|
T11 |
12605 |
|
T12 |
237 |
| auto[1] |
auto[1] |
auto[1] |
407459 |
1 |
|
|
T11 |
2321 |
|
T12 |
48 |
|
T17 |
3173 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8456632 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
79 |
| auto[1] |
6333086 |
1 |
|
|
T1 |
68 |
|
T11 |
31282 |
|
T12 |
563 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13976844 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
147 |
| auto[1] |
812874 |
1 |
|
|
T11 |
5104 |
|
T12 |
108 |
|
T17 |
7236 |