Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8422290 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
95 |
| auto[1] |
6367428 |
1 |
|
|
T1 |
52 |
|
T11 |
33663 |
|
T12 |
193 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13982293 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
145 |
| auto[1] |
807425 |
1 |
|
|
T1 |
2 |
|
T11 |
5021 |
|
T12 |
75 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8476625 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
87 |
| auto[1] |
6313093 |
1 |
|
|
T1 |
60 |
|
T11 |
31673 |
|
T12 |
356 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2756173 |
1 |
|
|
T1 |
39 |
|
T11 |
12075 |
|
T12 |
223 |
| auto[1] |
auto[0] |
auto[1] |
404126 |
1 |
|
|
T1 |
1 |
|
T11 |
2330 |
|
T12 |
59 |
| auto[1] |
auto[1] |
auto[0] |
2749495 |
1 |
|
|
T1 |
19 |
|
T11 |
14577 |
|
T12 |
58 |
| auto[1] |
auto[1] |
auto[1] |
403299 |
1 |
|
|
T1 |
1 |
|
T11 |
2691 |
|
T12 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |