Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8460288 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
86 |
| auto[1] |
6329430 |
1 |
|
|
T1 |
61 |
|
T11 |
31119 |
|
T12 |
421 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13977690 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
146 |
| auto[1] |
812028 |
1 |
|
|
T1 |
1 |
|
T11 |
5136 |
|
T12 |
91 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8463604 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
110 |
| auto[1] |
6326114 |
1 |
|
|
T1 |
37 |
|
T11 |
32502 |
|
T12 |
493 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2762981 |
1 |
|
|
T1 |
16 |
|
T11 |
13546 |
|
T12 |
190 |
| auto[1] |
auto[0] |
auto[1] |
406656 |
1 |
|
|
T1 |
1 |
|
T11 |
2637 |
|
T12 |
43 |
| auto[1] |
auto[1] |
auto[0] |
2751105 |
1 |
|
|
T1 |
20 |
|
T11 |
13820 |
|
T12 |
212 |
| auto[1] |
auto[1] |
auto[1] |
405372 |
1 |
|
|
T11 |
2499 |
|
T12 |
48 |
|
T17 |
3583 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |