Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8404475 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
121 |
| auto[1] |
6385243 |
1 |
|
|
T1 |
26 |
|
T11 |
31111 |
|
T12 |
515 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13982606 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
146 |
| auto[1] |
807112 |
1 |
|
|
T1 |
1 |
|
T11 |
4954 |
|
T12 |
88 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8494218 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
100 |
| auto[1] |
6295500 |
1 |
|
|
T1 |
47 |
|
T11 |
31780 |
|
T12 |
474 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2736376 |
1 |
|
|
T1 |
41 |
|
T11 |
13317 |
|
T12 |
165 |
| auto[1] |
auto[0] |
auto[1] |
401746 |
1 |
|
|
T1 |
1 |
|
T11 |
2443 |
|
T12 |
41 |
| auto[1] |
auto[1] |
auto[0] |
2752012 |
1 |
|
|
T1 |
5 |
|
T11 |
13509 |
|
T12 |
221 |
| auto[1] |
auto[1] |
auto[1] |
405366 |
1 |
|
|
T11 |
2511 |
|
T12 |
47 |
|
T17 |
3677 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |