Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8475183 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
105 |
| auto[1] |
6314535 |
1 |
|
|
T1 |
42 |
|
T11 |
31641 |
|
T12 |
410 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13975593 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
147 |
| auto[1] |
814125 |
1 |
|
|
T11 |
5137 |
|
T12 |
67 |
|
T17 |
6448 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8443672 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
100 |
| auto[1] |
6346046 |
1 |
|
|
T1 |
47 |
|
T11 |
32017 |
|
T12 |
357 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2776957 |
1 |
|
|
T1 |
33 |
|
T11 |
13107 |
|
T12 |
139 |
| auto[1] |
auto[0] |
auto[1] |
410067 |
1 |
|
|
T11 |
2542 |
|
T12 |
33 |
|
T17 |
3105 |
| auto[1] |
auto[1] |
auto[0] |
2754964 |
1 |
|
|
T1 |
14 |
|
T11 |
13773 |
|
T12 |
151 |
| auto[1] |
auto[1] |
auto[1] |
404058 |
1 |
|
|
T11 |
2595 |
|
T12 |
34 |
|
T17 |
3343 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |