Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8479099 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
97 |
| auto[1] |
6310619 |
1 |
|
|
T1 |
50 |
|
T11 |
31871 |
|
T12 |
695 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12163276 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
140 |
| auto[1] |
2626442 |
1 |
|
|
T1 |
7 |
|
T11 |
14028 |
|
T12 |
155 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8431451 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
105 |
| auto[1] |
6358267 |
1 |
|
|
T1 |
42 |
|
T11 |
31340 |
|
T12 |
320 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1871070 |
1 |
|
|
T1 |
17 |
|
T11 |
8597 |
|
T12 |
24 |
| auto[1] |
auto[0] |
auto[1] |
1317345 |
1 |
|
|
T1 |
5 |
|
T11 |
6838 |
|
T12 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1860755 |
1 |
|
|
T1 |
18 |
|
T11 |
8715 |
|
T12 |
141 |
| auto[1] |
auto[1] |
auto[1] |
1309097 |
1 |
|
|
T1 |
2 |
|
T11 |
7190 |
|
T12 |
148 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |