Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8457703 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
85 |
| auto[1] |
6332015 |
1 |
|
|
T1 |
62 |
|
T11 |
31282 |
|
T12 |
581 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12156333 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
118 |
| auto[1] |
2633385 |
1 |
|
|
T1 |
29 |
|
T11 |
14543 |
|
T12 |
257 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8424319 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
109 |
| auto[1] |
6365399 |
1 |
|
|
T1 |
38 |
|
T11 |
32547 |
|
T12 |
558 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1873838 |
1 |
|
|
T1 |
4 |
|
T11 |
8824 |
|
T12 |
105 |
| auto[1] |
auto[0] |
auto[1] |
1316477 |
1 |
|
|
T1 |
16 |
|
T11 |
7265 |
|
T12 |
86 |
| auto[1] |
auto[1] |
auto[0] |
1858176 |
1 |
|
|
T1 |
5 |
|
T11 |
9180 |
|
T12 |
196 |
| auto[1] |
auto[1] |
auto[1] |
1316908 |
1 |
|
|
T1 |
13 |
|
T11 |
7278 |
|
T12 |
171 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |