Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8440976 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
97 |
| auto[1] |
6348742 |
1 |
|
|
T1 |
50 |
|
T11 |
31459 |
|
T12 |
506 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12157461 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
130 |
| auto[1] |
2632257 |
1 |
|
|
T1 |
17 |
|
T11 |
15057 |
|
T12 |
244 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8434745 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
112 |
| auto[1] |
6354973 |
1 |
|
|
T1 |
35 |
|
T11 |
33440 |
|
T12 |
490 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1857423 |
1 |
|
|
T1 |
17 |
|
T11 |
8867 |
|
T12 |
67 |
| auto[1] |
auto[0] |
auto[1] |
1313038 |
1 |
|
|
T1 |
8 |
|
T11 |
7549 |
|
T12 |
62 |
| auto[1] |
auto[1] |
auto[0] |
1865293 |
1 |
|
|
T1 |
1 |
|
T11 |
9516 |
|
T12 |
179 |
| auto[1] |
auto[1] |
auto[1] |
1319219 |
1 |
|
|
T1 |
9 |
|
T11 |
7508 |
|
T12 |
182 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |