Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8468046 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
111 |
| auto[1] |
6321672 |
1 |
|
|
T1 |
36 |
|
T11 |
29680 |
|
T12 |
455 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12156966 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
124 |
| auto[1] |
2632752 |
1 |
|
|
T1 |
23 |
|
T11 |
14936 |
|
T12 |
213 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8422748 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
114 |
| auto[1] |
6366970 |
1 |
|
|
T1 |
33 |
|
T11 |
33801 |
|
T12 |
456 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1876165 |
1 |
|
|
T1 |
4 |
|
T11 |
10352 |
|
T12 |
131 |
| auto[1] |
auto[0] |
auto[1] |
1321604 |
1 |
|
|
T1 |
10 |
|
T11 |
8086 |
|
T12 |
103 |
| auto[1] |
auto[1] |
auto[0] |
1858053 |
1 |
|
|
T1 |
6 |
|
T11 |
8513 |
|
T12 |
112 |
| auto[1] |
auto[1] |
auto[1] |
1311148 |
1 |
|
|
T1 |
13 |
|
T11 |
6850 |
|
T12 |
110 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |