Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8469262 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
110 |
| auto[1] |
6320456 |
1 |
|
|
T1 |
37 |
|
T11 |
31245 |
|
T12 |
586 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12157389 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
128 |
| auto[1] |
2632329 |
1 |
|
|
T1 |
19 |
|
T11 |
12624 |
|
T12 |
146 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8442943 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
110 |
| auto[1] |
6346775 |
1 |
|
|
T1 |
37 |
|
T11 |
29210 |
|
T12 |
324 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1857723 |
1 |
|
|
T1 |
18 |
|
T11 |
8454 |
|
T12 |
50 |
| auto[1] |
auto[0] |
auto[1] |
1318394 |
1 |
|
|
T1 |
14 |
|
T11 |
6459 |
|
T12 |
61 |
| auto[1] |
auto[1] |
auto[0] |
1856723 |
1 |
|
|
T11 |
8132 |
|
T12 |
128 |
|
T17 |
10708 |
| auto[1] |
auto[1] |
auto[1] |
1313935 |
1 |
|
|
T1 |
5 |
|
T11 |
6165 |
|
T12 |
85 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |