Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8451425 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
93 |
| auto[1] |
6338293 |
1 |
|
|
T1 |
54 |
|
T11 |
32419 |
|
T12 |
579 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2788783 |
1 |
|
|
T1 |
16 |
|
T11 |
13455 |
|
T12 |
181 |
| auto[1] |
auto[0] |
auto[1] |
410507 |
1 |
|
|
T11 |
2459 |
|
T12 |
38 |
|
T17 |
3515 |
| auto[1] |
auto[1] |
auto[0] |
2736636 |
1 |
|
|
T1 |
38 |
|
T11 |
13860 |
|
T12 |
290 |
| auto[1] |
auto[1] |
auto[1] |
402367 |
1 |
|
|
T11 |
2645 |
|
T12 |
70 |
|
T17 |
3721 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |