Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8437382 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
116 |
| auto[1] |
6352336 |
1 |
|
|
T1 |
31 |
|
T11 |
31925 |
|
T12 |
318 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12159408 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
122 |
| auto[1] |
2630310 |
1 |
|
|
T1 |
25 |
|
T11 |
14357 |
|
T12 |
180 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8431233 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
107 |
| auto[1] |
6358485 |
1 |
|
|
T1 |
40 |
|
T11 |
32564 |
|
T12 |
380 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1861591 |
1 |
|
|
T1 |
12 |
|
T11 |
8847 |
|
T12 |
117 |
| auto[1] |
auto[0] |
auto[1] |
1313596 |
1 |
|
|
T1 |
19 |
|
T11 |
7068 |
|
T12 |
104 |
| auto[1] |
auto[1] |
auto[0] |
1866584 |
1 |
|
|
T1 |
3 |
|
T11 |
9360 |
|
T12 |
83 |
| auto[1] |
auto[1] |
auto[1] |
1316714 |
1 |
|
|
T1 |
6 |
|
T11 |
7289 |
|
T12 |
76 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |