Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8439141 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
92 |
| auto[1] |
6350577 |
1 |
|
|
T1 |
55 |
|
T11 |
30918 |
|
T12 |
315 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12167264 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
109 |
| auto[1] |
2622454 |
1 |
|
|
T1 |
38 |
|
T11 |
13177 |
|
T12 |
209 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8471827 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
100 |
| auto[1] |
6317891 |
1 |
|
|
T1 |
47 |
|
T11 |
30449 |
|
T12 |
401 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1852817 |
1 |
|
|
T1 |
3 |
|
T11 |
8802 |
|
T12 |
140 |
| auto[1] |
auto[0] |
auto[1] |
1314582 |
1 |
|
|
T1 |
25 |
|
T11 |
6570 |
|
T12 |
145 |
| auto[1] |
auto[1] |
auto[0] |
1842620 |
1 |
|
|
T1 |
6 |
|
T11 |
8470 |
|
T12 |
52 |
| auto[1] |
auto[1] |
auto[1] |
1307872 |
1 |
|
|
T1 |
13 |
|
T11 |
6607 |
|
T12 |
64 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |