Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8446488 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
118 |
| auto[1] |
6343230 |
1 |
|
|
T1 |
29 |
|
T11 |
32691 |
|
T12 |
388 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12161926 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
134 |
| auto[1] |
2627792 |
1 |
|
|
T1 |
13 |
|
T11 |
13449 |
|
T12 |
188 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8455726 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
95 |
| auto[1] |
6333992 |
1 |
|
|
T1 |
52 |
|
T11 |
30911 |
|
T12 |
352 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1857530 |
1 |
|
|
T1 |
30 |
|
T11 |
8202 |
|
T12 |
83 |
| auto[1] |
auto[0] |
auto[1] |
1319054 |
1 |
|
|
T1 |
11 |
|
T11 |
6588 |
|
T12 |
106 |
| auto[1] |
auto[1] |
auto[0] |
1848670 |
1 |
|
|
T1 |
9 |
|
T11 |
9260 |
|
T12 |
81 |
| auto[1] |
auto[1] |
auto[1] |
1308738 |
1 |
|
|
T1 |
2 |
|
T11 |
6861 |
|
T12 |
82 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |