Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8435310 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
85 |
| auto[1] |
6354408 |
1 |
|
|
T1 |
62 |
|
T11 |
30853 |
|
T12 |
200 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12144393 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
136 |
| auto[1] |
2645325 |
1 |
|
|
T1 |
11 |
|
T11 |
13824 |
|
T12 |
184 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8395816 |
1 |
|
|
T33 |
1496 |
|
T34 |
232 |
|
T1 |
116 |
| auto[1] |
6393902 |
1 |
|
|
T1 |
31 |
|
T11 |
31053 |
|
T12 |
363 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1875111 |
1 |
|
|
T1 |
8 |
|
T11 |
8984 |
|
T12 |
156 |
| auto[1] |
auto[0] |
auto[1] |
1324053 |
1 |
|
|
T1 |
7 |
|
T11 |
7077 |
|
T12 |
158 |
| auto[1] |
auto[1] |
auto[0] |
1873466 |
1 |
|
|
T1 |
12 |
|
T11 |
8245 |
|
T12 |
23 |
| auto[1] |
auto[1] |
auto[1] |
1321272 |
1 |
|
|
T1 |
4 |
|
T11 |
6747 |
|
T12 |
26 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |